A system on chip includes: a functional circuit configured to perform a processing operation by receiving a supply voltage; a droop detection circuit configured to monitor the supply voltage and generate a detection signal indicating whether a droop of the supply voltage has occurred; a clock generation circuit configured to output a first clock signal having a first frequency; and a clock modulation circuit configured to receive the detection signal and the first clock signal, and provide a system clock signal to the functional circuit.

An Information Handling System (IHS) includes multiple hardware devices, and a baseboard Management Controller (BMC) in communication with the plurality of hardware devices. The BMC includes executable instructions for when a custom BMC firmware stack is executed on the BMC, monitoring a parameter of one or more of the hardware devices of the IHS. The instructions that monitor the parameter are separate and distinct from the instructions of the custom BMC firmware stack. The instructions also controls the BMC to perform one or more operations to remediate an excessive parameter when the parameter exceeds a specified threshold.

In one or more embodiments, one or more systems, one or more methods, and/or one or more processes may receive first data from a first device via a first two-wire interface (TWI) bus; provide the first data to a second device via a second TWI bus; receive a first arbitration request via an out of band arbitration process from a third device; provide first control information via an in band arbitration process to the first device via the first TWI bus; receive second data from an isolation device via a third TWI bus; provide the second data to the second device via the second TWI bus; receive a second arbitration request via the in band arbitration process from the first device via the first TWI bus; and provide second control information via the out of band arbitration process to the third device.

This disclosure describes system on a chip (SOC) communications that prevent direct memory access (DMA) attacks. An example SoC includes an encryption engine and a security processor. The encryption engine is configured to encrypt raw input data using a cipher key to form an encrypted payload. The security processor is configured to select the cipher key from a key store holding a plurality of cipher keys based on a channel ID describing a {source subsystem, destination subsystem} tuple for the encrypted payload, to form an encryption header that includes the channel ID, to encapsulate the encrypted payload with the encryption header that includes the channel ID to form a crypto packet, and to transmit the crypto packet to a destination SoC that is external to the SoC.

An integrated circuit (IC) including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture. For example, the IC may include an interconnect fabric configured to provide communication between the one or more memory controller circuits and the processor cores, graphics processing units, and peripheral devices; and an off-chip interconnect coupled to the interconnect fabric and configured to couple the interconnect fabric to a corresponding interconnect fabric on another instance of the integrated circuit, wherein the interconnect fabric and the off-chip interconnect provide an interface that transparently connects the one or more memory controller circuits, the processor cores, graphics processing units, and peripheral devices in either a single instance of the integrated circuit or two or more instances of the integrated circuit.

In an embodiment, a system on a chip (SOC) comprises a semiconductor die on which circuitry is formed, wherein the circuitry comprises a memory controller circuit and a plurality of networks formed from a plurality of individual network component circuits. The memory controller includes a PIO message control circuit that is configured to receive PIO messages addressed to individual network component circuits and determine whether to send the PIO messages to the individual network component circuits based on determine whether previous PIO messages are pending for the individual network component circuits. The PIO message control circuit is configured to delay a first PIO message at the PIO message control circuit in response to determining that previous PIO message is pending for the addressee of the first PIO message.

Technologies for dynamic accelerator selection include a compute sled. The compute sled includes a network interface controller to communicate with a remote accelerator of an accelerator sled over a network, where the network interface controller includes a local accelerator and a compute engine. The compute engine is to obtain network telemetry data indicative of a level of bandwidth saturation of the network. The compute engine is also to determine whether to accelerate a function managed by the compute sled. The compute engine is further to determine, in response to a determination to accelerate the function, whether to offload the function to the remote accelerator of the accelerator sled based on the telemetry data. Also the compute engine is to assign, in response a determination not to offload the function to the remote accelerator, the function to the local accelerator of the network interface controller.

An embodiment of a qubit tuning device includes a first layer configured to generate a magnetic field, the first layer comprising a material exhibiting superconductivity in a cryogenic temperature range. In an embodiment, the qubit tuning device includes a qubit of a quantum processor chip, wherein the first layer is configured to magnetically interact with the qubit such that a first magnetic flux of the first layer causes a first change in a first resonance frequency of the qubit by a first frequency shift value.

Methods and apparatus are disclosed to protect secure assets using scan operations. One example apparatus includes logic circuitry including a scan chain that includes data storage elements and design logic coupled to the scan chain. The example apparatus also includes data storage to store secure data. The design logic is coupled to the data storage. The example apparatus also includes a security controller to transition the apparatus out of a secure mode of operation. The transition includes the security controller to cause the scan chain to serially shift secure scan data from an input of the scan chain into each data storage element of the data storage elements of the scan chain.

An operation method of a sleep mode of an electronic device includes the following steps. A first sub-module of a first module sends a sleep command to a second sub-module of the first module and a third sub-module and a fourth sub-module of a second module, wherein the first sub-module includes first and second modes, the second sub-module includes third and fourth nodes, the third sub-module includes fifth and sixth nodes, and the fourth sub-module includes seventh and eighth nodes. The second sub-module, the third sub-module and fourth sub-module execute a sleep sequence in sequence to enter a sleep mode according to the sleep command. The first node sends the sleep command to the second node to execute the sleep sequence to enter the sleep mode. The first node sends the sleep command to the first node to execute the sleep sequence to enter the sleep mode.