Embodiments herein describe a processor system that includes an integrated, adaptive accelerator. In one embodiment, the processor system includes multiple core complex chiplets that each contain one or processing cores for a host CPU. In addition the processor system includes an accelerator chiplet. The processor system can assign one or more of the core complex chiplets to the accelerator chiplet to form an IO device while the remaining core complex chiplets form the CPU for the host. In this manner, rather than the accelerator and the CPU having independent computer resources, the accelerator can be integrated into the processor system of the host so that hardware resources can be divided between the CPU and the accelerator depending on the needs of the particular application(s) executed by the host.

Disclosed in some examples, are methods, systems, programmable atomic units, and machine-readable mediums that provide an exception as a response to the calling processor. That is, the programmable atomic unit will send a response to the calling processor. The calling processor will recognize that the exception has been raised and will handle the exception. Because the calling processor knows which process triggered the exception, the calling processor (e.g., the Operating System) can take appropriate action, such as terminating the calling process. The calling processor may be a same processor as that executing the programmable atomic transaction, or a different processor (e.g., on a different chiplet).

In one aspect of the present disclosure, a data storage and processing system is provided. The system includes a host server and a storage unit. The storage unit includes a drive comprising a memory and a drive processor, an external switch configured to couple the host server to the drive to send and receive data between the host server and the memory of the drive and a graphics processing unit. The drive processor is configured to send processing instructions and data from the drive memory to the graphics processing unit and the graphics processing unit is configured to process the data according to the processing instructions to generate result data.

Secure IoT devices and methods of use are disclosed herein. An example Internet-of-Things (IoT) device includes an interface for transmitting and receiving data on a network; and a chip comprising a reconfigurable hardware core configured to transmit the data using the interface. The reconfigurable hardware core is not vulnerable to malicious attacks can be used to replace a central processing unit (CPU) which is vulnerable to malicious attacks.

An example system may comprise a network-attached storage device including a base station having a hardware interface including a drive port and a connectivity port; a modular storage drive attachable to and detachable from the drive port; and a modular wireless adapter attachable to and detachable from the connectivity port. The portable storage device is formable by detaching the modular storage drive and the modular wireless adapter from the hardware interface of the network-attached storage device, and coupling the modular storage drive and the modular wireless adapter to one another via a portable hardware interface. Further, a rechargeable modular power unit is removable from the base station and attachable to and detachable from a power port of the network-attached storage device.

Apparatus and methods for processing neural network models are provided. The apparatus can comprise a plurality of identical artificial intelligence processing dies. Each artificial intelligence processing die among the plurality of identical artificial intelligence processing dies can include at least one inter-die input block and at least one inter-die output block. Each artificial intelligence processing die among the plurality of identical artificial intelligence processing dies is communicatively coupled to another artificial intelligence processing die among the plurality of identical artificial intelligence processing dies by way of one or more communication paths from the at least one inter-die output block of the artificial intelligence processing die to the at least one inter-die input block of the artificial intelligence processing die. Each artificial intelligence processing die among the plurality of identical artificial intelligence processing dies corresponds to at least one layer of a neural network.

Aspects of the disclosure are directed to a heterogeneous machine learning accelerator system with compute and memory nodes connected by high speed chip-to-chip interconnects. While existing remote/disaggregated memory may require memory expansion via remote processing units, aspects of the disclosure add memory nodes into machine learning accelerator clusters via the chip-to-chip interconnects without needing assistance from remote processing units to achieve higher performance, simpler software stack, and/or lower cost. The memory nodes may support prefetch and intelligent compression to enable the use of low cost memory without performance degradation.

In a general aspect, a quantum processor has a modular architecture. In some aspects, a modular quantum processor includes first and second quantum processor chips and a cap structure. The first quantum processor chip is supported on a substrate layer and includes a first plurality of qubit devices. The second quantum processor chip is supported on the substrate layer and includes a second plurality of qubit devices. The cap structure is supported on the first and second quantum processor chips and includes a coupler device that provides coupling between at least one of the first plurality of qubit devices with at least one of the second plurality of qubit devices. In some instances, the coupler device is an active coupler device that is configured to selectively couple at least one of the first plurality of qubit devices with at least one of the second plurality of qubit devices.

Provided efficiently and at low cost are: a package for core number ratios appropriate for all types of computers; and dies included in the package.

This package includes at least one die provided with: at least one of a first core formed of a CPU core or a latency core and a second core formed of an accelerator core or a throughput core; an external interface; memory interfaces 24 to 26; and a die interface 23 which is connected to another die.

The die includes a first type die and a second type die each including both the first core and the second core and the core number ratio between the first core and the second core in the first type die differs from that in the second type die.

Moreover, the memory interfaces include an interface conforming to TCI.

In addition, the memory interfaces further include an interface conforming to HBM.

In one aspect of the present disclosure, a data storage and processing system is provided. The system includes a host server and a storage unit. The storage unit includes a drive comprising a memory and a drive processor, an external switch configured to couple the host server to the drive to send and receive data between the host server and the memory of the drive and a graphics processing unit. The drive processor is configured to send processing instructions and data from the drive memory to the graphics processing unit and the graphics processing unit is configured to process the data according to the processing instructions to generate result data.