Aspects of the disclosure are directed to a heterogeneous machine learning accelerator system with compute and memory nodes connected by high speed chip-to-chip interconnects. While existing remote/disaggregated memory may require memory expansion via remote processing units, aspects of the disclosure add memory nodes into machine learning accelerator clusters via the chip-to-chip interconnects without needing assistance from remote processing units to achieve higher performance, simpler software stack, and/or lower cost. The memory nodes may support prefetch and intelligent compression to enable the use of low cost memory without performance degradation.

In a general aspect, a quantum processor has a modular architecture. In some aspects, a modular quantum processor includes first and second quantum processor chips and a cap structure. The first quantum processor chip is supported on a substrate layer and includes a first plurality of qubit devices. The second quantum processor chip is supported on the substrate layer and includes a second plurality of qubit devices. The cap structure is supported on the first and second quantum processor chips and includes a coupler device that provides coupling between at least one of the first plurality of qubit devices with at least one of the second plurality of qubit devices. In some instances, the coupler device is an active coupler device that is configured to selectively couple at least one of the first plurality of qubit devices with at least one of the second plurality of qubit devices.

A system and method for enabling reconfigurable and flexible modular compute (M). The environment (100) may include modular system (M) including a first modular system (M1), a second modular system (M2), peripheral equipments (105), a network (107), and optionally, remote user device (109). The method includes placing at least one first reconfigurable block of one or more reconfigurable blocks on a first modular platform, placing at least one second reconfigurable block of one or more reconfigurable blocks on a second modular platform, placing a plurality of components surrounding the first reconfigurable block and the second reconfigurable block on respective the first modular platform and the second modular platform, configuring one or more interconnections between the plurality of components to form a modular network.

Various aspects of the present disclosure generally relate to integrated circuits. In some aspects, a device may include a plurality of modules. The device may indicate, via a module of the plurality of modules and during an initialization parameter exchange, whether the module supports a flexible module configuration that enables the module to be interfaced with another module associated with a different configuration than the module. The device may configure, via a multi-module physical logic and based on the initialization parameter exchange, an interfacing between a first set of modules, of the plurality of modules, and a second set of modules, of the plurality of modules, wherein the interfacing is configured based at least in part on a first configuration associated with the first set of modules and a second configuration associated with the second set of modules that is different from the first configuration. Numerous other aspects are described.

Examples described herein relate to a device that includes: a plurality of nodes, wherein a node of the plurality of nodes comprises at least one processor and a structure comprising multiple physical layers, wherein different physical layers of the multiple physical layers are to provide communication entry points to at least some of the same nodes at different node spans by a stack of overlapping two dimensional (2D) meshes. In some examples, a first layer of the multiple layers comprises a first trace that comprises a link that connects a first span of nodes. In some examples, a second layer of the multiple layers comprises a second trace that comprises a link that connects a second span of nodes, where the first span of nodes is greater than the second span of nodes.

Embodiments herein describe a processor system that includes an integrated, adaptive accelerator. In one embodiment, the processor system includes multiple core complex chiplets that each contain one or processing cores for a host CPU. In addition the processor system includes an accelerator chiplet. The processor system can assign one or more of the core complex chiplets to the accelerator chiplet to form an IO device while the remaining core complex chiplets form the CPU for the host. In this manner, rather than the accelerator and the CPU having independent computer resources, the accelerator can be integrated into the processor system of the host so that hardware resources can be divided between the CPU and the accelerator depending on the needs of the particular application(s) executed by the host.