G06F17/12

Window Function Processing Module
20180013410 · 2018-01-11 ·

The present application provides a window function processing module including an integrating circuit, configured to receive an integrating input signal, the integrating circuit comprising an operational amplifier; an integrating capacitor, coupled to an output terminal and a first input terminal of the operational amplifier; and an adjustable impedance module, coupled between the first input terminal of the operational amplifier and an integrating input terminal of the integrating circuit, wherein the adjustable impedance module is controlled by at least one control signal to adjust an impedance value of the adjustable impedance module; and a control unit, coupled to the integrating circuit, configured to generate the at least one control signal according to a window function, to adjust the integration gain of the integrating circuit, such that the integrating output signal is related to an operation result of the integrating input signal and the window function.

Product decomposition of periodic functions in quantum signal processing
11568295 · 2023-01-31 · ·

In some embodiments, one or more unitary-valued functions are generated by a classical computer generating using projectors with a predetermined number of significant bits. A quantum computing device is then configured to implement the one or more unitary-valued functions. In further embodiments, a quantum circuit description for implementing quantum signal processing that decomposes complex-valued periodic functions is generated by a classical computer, wherein the generating further includes representing approximate polynomials in a Fourier series with rational coefficients. A quantum computing device is then configured to implement a quantum circuit defined by the quantum circuit description.

Product decomposition of periodic functions in quantum signal processing
11568295 · 2023-01-31 · ·

In some embodiments, one or more unitary-valued functions are generated by a classical computer generating using projectors with a predetermined number of significant bits. A quantum computing device is then configured to implement the one or more unitary-valued functions. In further embodiments, a quantum circuit description for implementing quantum signal processing that decomposes complex-valued periodic functions is generated by a classical computer, wherein the generating further includes representing approximate polynomials in a Fourier series with rational coefficients. A quantum computing device is then configured to implement a quantum circuit defined by the quantum circuit description.

ZERO-COPY SPARSE MATRIX FACTORIZATION SYNTHESIS FOR HETEROGENEOUS COMPUTE SYSTEMS
20230024035 · 2023-01-26 ·

A system, method, and computer-readable medium for synthesizing zero-copy sparse matrix factorization operations in heterogeneous compute systems are provided. The system includes a host and an accelerator device. The host device is configured to divide an input matrix into a plurality of blocks which are transferred to a memory of the accelerator device. The host device is also configured to generate at least one index buffer that includes pointers to the block in the accelerator's memory, where each index buffer represents a frontal matrix associated with a matrix decomposition algorithm. The host processor is configured to receive one or more kernels configured to process the index buffer(s) on an accelerator device. The index buffers are processed by the accelerator device and the modified block data is written back to a memory of the host device to generate a factorized output matrix.

ZERO-COPY SPARSE MATRIX FACTORIZATION SYNTHESIS FOR HETEROGENEOUS COMPUTE SYSTEMS
20230024035 · 2023-01-26 ·

A system, method, and computer-readable medium for synthesizing zero-copy sparse matrix factorization operations in heterogeneous compute systems are provided. The system includes a host and an accelerator device. The host device is configured to divide an input matrix into a plurality of blocks which are transferred to a memory of the accelerator device. The host device is also configured to generate at least one index buffer that includes pointers to the block in the accelerator's memory, where each index buffer represents a frontal matrix associated with a matrix decomposition algorithm. The host processor is configured to receive one or more kernels configured to process the index buffer(s) on an accelerator device. The index buffers are processed by the accelerator device and the modified block data is written back to a memory of the host device to generate a factorized output matrix.

Analysis/synthesis windowing function for modulated lapped transformation

There are provided methods and apparatus for performing modified cosine transformation (MDCT) with an analysis/synthesis windowing function, using an analysis windowing function having a meandering portion which passes a linear function in correspondence of at least four points.

Analysis/synthesis windowing function for modulated lapped transformation

There are provided methods and apparatus for performing modified cosine transformation (MDCT) with an analysis/synthesis windowing function, using an analysis windowing function having a meandering portion which passes a linear function in correspondence of at least four points.

SIGNAL-CHARGE ESTIMATOR AND METHOD
20230224603 · 2023-07-13 ·

A method for estimating a signal charge collected by a pixel of an image sensor includes determining an average bias that depends on the pixel's floating-diffusion dark current and pixel-sampling period. The method also includes determining a signal-charge estimate as the average bias subtracted from a difference between a weighted sum of a plurality of N multiple-sampling values each multiplied by a respective one of a plurality of N sample-weights.

SIGNAL-CHARGE ESTIMATOR AND METHOD
20230224603 · 2023-07-13 ·

A method for estimating a signal charge collected by a pixel of an image sensor includes determining an average bias that depends on the pixel's floating-diffusion dark current and pixel-sampling period. The method also includes determining a signal-charge estimate as the average bias subtracted from a difference between a weighted sum of a plurality of N multiple-sampling values each multiplied by a respective one of a plurality of N sample-weights.

Conversion of Pauli errors to erasure errors in a photonic quantum computing system
11558069 · 2023-01-17 · ·

A quantum computing system for converting Pauli errors of one or more qubits to erasure errors in a photonic quantum computing architecture. Two or more photonic qubits may be input to a quantum computing system, where at least one first qubit of the two or more qubits has experienced a Pauli error. A sequence of linear optical circuitry operations may be performed on the two or more qubits to generate two or more modified qubits, wherein the sequence of operations transforms one or more of the first qubits from a logical subspace of a Fock space to an erasure subspace of the Fock space. A cluster state for universal quantum computing may be generated from the two or more modified qubits using probabilistic entangling gates. A quantum computational algorithm may be performed using the quantum cluster state generated from the two or more modified qubits.