A signal processor is configured to perform a process equivalent to performing a series of fixed-to-rotating coordinate conversion, a predetermined process and then rotating-to-fixed coordinate conversion, while maintaining linearity and time-invariance. The signal processor performs a process given by the following matrix G:

[00001]$G=\left[\begin{array}{cc}\frac{F\left(s+j{\omega }_0\right)+F\left(s-j{\omega }_0\right)}{2}& \frac{F\left(s+j{\omega }_0\right)-F\left(s-j{\omega }_0\right)}{2}\\ -\frac{F\left(s+j{\omega }_0\right)-F\left(s-j{\omega }_0\right)}{2j}& \frac{F\left(s+j{\omega }_0\right)+F\left(s-j{\omega }_0\right)}{2}\end{array}\right]$

where F(s) is a transfer function representing the predetermined process, ω.sub.0 is a predetermined angular frequency and j is the imaginary unit.

A method and apparatus for decoding a video sequence using a discrete sine transform (DST) type-VII transform core includes generating a set of tuples of transform core elements associated with an n-point DST-VII transform core. A first sum of a first subset of transform core elements of a first tuple is equal to a second sum of a second subset of remaining transform core elements of the first tuple. The n-point DST-VII transform core is generated based on generating the set of tuples of transform core elements. A transform on a block is performed using the n-point DST-VII transform core.

The present disclosure discloses an image decompression method, device, and display terminal. The method includes: a step of acquiring image compression data; a step of performing inverse quantization on the image compression data based on a preset inverse quantization factor to obtain inversely quantized data; wherein the inverse quantization factor is in integer form; and a step of performing an inverse discrete cosine transformation (DCT) on the inversely quantized data to obtain image data; wherein the inverse DCT includes bit-shift operations and addition operations.

A method for decoding an encoded video bit stream in a video decoder is provided that includes determining a scan pattern type for a transform block to be decoded, decoding a column position X and a row position Y of a last non-zero coefficient in the transform block from the encoded video bit stream, selecting a column-row inverse transform order when the scan pattern type is a first type, selecting a row-column inverse transform order when the scan pattern type is a second type, and performing one dimensional (1D) inverse discrete cosine transformation (IDCT) computations according to the selected transform order to inversely transform the transform block to generate a residual block.

A signal processor is configured to perform a process equivalent to performing a series of fixed-to-rotating coordinate conversion, a predetermined process and then rotating-to-fixed coordinate conversion, while maintaining linearity and time-invariance. The signal processor performs a process given by the following matrix G: $G=[\begin{array}{cc}\frac{F\left(s+j{\omega }_0\right)+F\left(s-j{\omega }_0\right)}{2}& \frac{F(s+j{\omega }_0}{}\end{array}$

A video data encoding method for encoding an array of video data values includes frequency-transforming the video data values according to a frequency transform, to generate an array of frequency-transformed values by a matrix-multiplication process using a transform matrix having a data precision greater than six bits.

The present application discloses a verification system and method for an operation result based on a reconfigurable butterfly unit. The system is applicable to a digital signal processing (DSP) chip. The DSP chip includes a reconfigurable butterfly unit. The reconfigurable butterfly unit may be reconfigured into two modes: a first verification mode and a second verification mode. The system includes: a controller, a memory, a verification unit, a first data gating unit, and a second data gating unit. The technical solution in the present application is used to overcome the disadvantage that an existing verification system and an existing verification method consume large hardware resources, thereby reducing the implementation costs of operation result verification.

A method, computer program, and computer system is provided for coding video data. Video data is received. One or more transform cores corresponding to a transform associated with the video data are identified. The one or more transform cores include one or more of a line graph transform (LGT) and a discrete cosine transform (DCT) The video data is decoded based on the identified transform core. The transform cores correspond to one or more from among an 8-bit transform core and a 10-bit transform core. The transform corresponds to one or more from among a 2-point transform, a 4-point transform, an 8-point transform, a 16-point transform, a 32-point transform, and a 64-point transform.

A method, computer program, and computer system is provided for coding video data. Video data is received. One or more transform cores corresponding to a transform associated with the video data are identified. The one or more transform cores include one or more of a line graph transform (LGT) and a discrete sine transform (DST) The video data is decoded based on the identified transform core. The transform cores correspond to one or more from among an 8-bit transform core and a 10-bit transform core. The transform corresponds to one or more from among a 2-point transform, a 4-point transform, an 8-point transform, and a 16-point transform.

Methods and apparatus for performing video processing matrix operations within a memory fabric. Various embodiments of the present disclosure are directed to converting a memory array into a matrix fabric for discrete cosine transform (DCT) matrix transformations and performing DCT matrix operations therein. Exemplary embodiments described herein perform DCT matrix-matrix multiplication operations within a memory device that includes a matrix fabric and matrix multiplication unit (MMU). In one embodiment, matrix-matrix multiplication operations are obtained using separate matrix-vector products. In one exemplary embodiment, the matrix fabric uses a “crossbar” construction of resistive elements. Each resistive element stores a level of impedance that represents the corresponding matrix coefficient value. The crossbar connectivity can be driven with an electrical signal representing the input vector as an analog voltage. The resulting signals can be converted from analog voltages to a digital values by an MMU to yield a vector-matrix product. In some cases, the MMU may additionally perform various other logical operations within the digital domain.