Methods and systems for performing a convolution transpose operation between an input tensor having a plurality of input elements and a filter comprising a plurality of filter weights. The method includes: dividing the filter into a plurality of sub-filters; performing, using hardware logic, a convolution operation between the input tensor and each of the plurality of sub-filters to generate a plurality of sub-output tensors, each sub-output tensor comprising a plurality of output elements; and interleaving, using hardware logic, the output elements of the plurality of sub-output tensors to form a final output tensor for the convolution transpose.

An information processing apparatus stores mesh data including a plurality of nodes and a plurality of edges and boundary condition data indicating force applied to an object represented by the mesh data. The information processing apparatus calculates a stiffness matrix including a plurality of stiffness values corresponding to the plurality of edges and a force vector including a plurality of force values corresponding to the plurality of nodes. The information processing apparatus generates feature data from the stiffness matrix and the force vector. The information processing apparatus infers a plurality of displacement amounts corresponding to the plurality of nodes by performing a convolutional operation on the feature data in accordance with a connection relationship of the plurality of nodes.

A memory of an electronic device stores three-dimensional input data comprising (i) input values, (ii) first kernel information, and (iii) second kernel information. The processor includes multiplication modules corresponding to the channels and performs a convolution operation based on the input values and the weights through the multiplication modules. Based on a depthwise convolution operation, a processor of the electronic device controls an input selection module to (a) configure the input values to correspond to a first channel among the channels and (b) input the input values to two or more multiplication modules among the multiplication modules. The processor inputs weights, obtains intermediate values, and obtains output values based on each of a summed result by summing intermediate values respectively corresponding to locations of the kernels from among the intermediate values through a first intermediate value accumulation module.

Described herein are computer-implemented methods for compressing sparse multidimensional ordered series data. In particular, these methods and apparatuses for performing them (including software) may be particularly well suited to efficiently compressing spectrographic data.

A system and method of executing a convolution layer of a neural network may include: (a) selecting an output spatial position (OSP) of an output matrix data element of the convolution layer; (b) selecting, based on the selected OSP, a non-zero input element of an input matrix data element; (c) producing, based on the selected OSP, a vector of kernel elements from a kernel matrix data element; (d) performing a vectoral multiplication operation of the selected non-zero input element and the vector of kernel elements, and accumulating a product of the vectoral multiplication in a vector register of a processor; (e) repeating (c) and (d) with subsequent non-zero input elements and corresponding vectors of kernel elements to obtain an outcome of the convolution of the selected OSP; and (f) repeating (a) through (e) with subsequent selection of OSPs, to obtain an outcome of the convolution layer.

The present disclosure provides a winograd convolution operation method, a winograd convolution operation apparatus, a device, and a storage medium. The apparatus includes: processors and a memory, where the memory is configured to store a program code, and the processors are configured to call the program code stored in the memory and execute the operation method. Through the operation method, a system, the device and the storage medium of the present disclosure, performance loss of a computer system may be reduced, and operation speed may be improved. Through the present disclosure, processing efficiency may be improved.

A monolithic integrated circuit (IC) including one or more compute circuitry, one or more non-volatile memory circuits, one or more communication channels and one or more communication interface. The one or more communication channels can communicatively couple the one or more compute circuitry, the one or more non-volatile memory circuits and the one or more communication interface together. The one or more communication interfaces can communicatively couple one or more circuits of the monolithic integrated circuit to one or more circuits external to the monolithic integrated circuit.

A processor system comprises a first and second group of registers and a hardware channel convolution processor unit. The first group of registers is configured to store data elements of channels of a portion of a convolution data matrix. Each register stores at least one data element from each channel. The second group of registers is configured to store data elements of convolution weight matrices including a separate convolution weight matrix for each channel. Each register stores at least one data element from each convolution weight matrix. The hardware channel convolution processor unit is configured to multiply each data element in the first group of registers with a corresponding data element in the second group of registers and sum together the multiplication results for each specific channel to determine corresponding channel convolution result data elements in a corresponding channel convolution result matrix.

This disclosure relates to a data processing method, a data processing apparatus, and related products. The products include a control unit. The control unit includes: an instruction caching unit, an instruction processing unit, and a storage queue unit. The instruction caching unit is used for storing a calculation instruction associated with an artificial neural network computation; the instruction processing unit is used for parsing the calculation instruction to obtain a plurality of computation instructions; and the storage queue unit is used for storing an instruction queue, where the instruction queue includes the plurality of computation instructions or calculation instructions to be executed according to a front-back sequence of a queue. Through the above method of this disclosure, computation efficiency of the related products during a neural network model computation may be improved.

Disclosed are a weight data storage method and a convolution computation method that may be implemented in a neural network. The weight data storage method comprises searching for effective weights in a weight convolution kernel matrix and acquiring an index of effective weights. The effective weights are non-zero weights, and the index of effective weights is used to mark the position of the effective weights in the weight convolution kernel matrix. The weight data storage method further comprises storing the effective weights and the index of effective weights. According to the weight data storage method and the convolution computation method of the present disclosure, storage space can be saved, and computation efficiency can be improved.