G06F21/74

MOBILE DEVICE WITH SECURE PRIVATE MEMORY

A mobile device can detect an idle state and, in response, initiate an access monitoring function to covertly monitor activity involving a human interaction with the mobile device. The covert monitoring is undetectable by a user of the mobile device. The mobile device can then detect a human interaction with the mobile device and, in response, cause the mobile device to covertly capture and log one or more human interactions with the mobile device. An authorized user of the mobile device is enabled to review the log of human interactions with the mobile device.

SYSTEM MANAGEMENT MODE RUNTIME RESILIENCY MANAGER
20230013235 · 2023-01-19 · ·

A system management mode (SMM) runtime resiliency manager (SRM) augments computing resource protection policies provided by an SMM policy shim The SMM shim protects system resources by deprivileging system management interrupt (SMI) handlers to a lower level of privilege (e.g., ring 3 privilege) and by configuring page tables and register bitmaps (e.g., I/O, MSR, and Save State register bitmaps). SRM capabilities include protecting the SMM shim, updating the SMM shim, protecting a computing system during SMM shim update, detecting SMM attacks, and recovering attacked or faulty SMM components.

PROTECTED CIRCUIT SYSTEM AND METHOD OF OPERATION
20230214536 · 2023-07-06 ·

Circuits are protected from timing attacks by adding a random delay to mask any relation between contents of processed information packages and the processing time required between in- and output signals of protected circuits. This random delay has to be performed preferably inside the protected volume and can be realized by one or more random delay buffers that are realized by means of e.g. random shift-registers. Further protection may be provided by situating the circuits in a single chip housing, such that the signals thereof interfere with each other and it is difficult to obtain information therefrom. A physical barrier may be provided in order to prevent or at least limit physical access to for example at least one TPM chip arranged inside of the barrier. The physical barrier comprises an impedance, i.e. in form of a capacitor with capacity C and or resistor R and or inductivity L, for example formed by two of the reflector layers of the barrier with an absorbing material in between. Any impedance (i.e. capacity C and/or resistance R and/or inductivity L) change can be detected and any impedance (i.e. capacity and/or resistance and/or inductivity L) change beyond a chosen threshold is indicative of an attempt to physically destruct or enter the barrier. Upon detecting an impedance (i.e. capacity C and/or resistance R and/or inductivity L) change beyond the threshold, any suitable action may be performed, such as deleting all information from the chip, destroying the chip or providing wrong information. The barrier may also act as a reflector for reflecting the desired signal of the at least one chip, such that the desired signal and the reflected signals interfere with each other and it is difficult to obtain information therefrom.

PROTECTED CIRCUIT SYSTEM AND METHOD OF OPERATION
20230214536 · 2023-07-06 ·

Circuits are protected from timing attacks by adding a random delay to mask any relation between contents of processed information packages and the processing time required between in- and output signals of protected circuits. This random delay has to be performed preferably inside the protected volume and can be realized by one or more random delay buffers that are realized by means of e.g. random shift-registers. Further protection may be provided by situating the circuits in a single chip housing, such that the signals thereof interfere with each other and it is difficult to obtain information therefrom. A physical barrier may be provided in order to prevent or at least limit physical access to for example at least one TPM chip arranged inside of the barrier. The physical barrier comprises an impedance, i.e. in form of a capacitor with capacity C and or resistor R and or inductivity L, for example formed by two of the reflector layers of the barrier with an absorbing material in between. Any impedance (i.e. capacity C and/or resistance R and/or inductivity L) change can be detected and any impedance (i.e. capacity and/or resistance and/or inductivity L) change beyond a chosen threshold is indicative of an attempt to physically destruct or enter the barrier. Upon detecting an impedance (i.e. capacity C and/or resistance R and/or inductivity L) change beyond the threshold, any suitable action may be performed, such as deleting all information from the chip, destroying the chip or providing wrong information. The barrier may also act as a reflector for reflecting the desired signal of the at least one chip, such that the desired signal and the reflected signals interfere with each other and it is difficult to obtain information therefrom.

PROCESSOR WITH NETWORK STACK DOMAIN AND SYSTEM DOMAIN USING SEPARATE MEMORY REGIONS
20230214535 · 2023-07-06 ·

The disclosed technology is generally directed to network security for processors. In one example of the technology, a computing device includes: a processor, a memory, and a network interface. The computing device executes a first binary within a first region of the memory, executes a separate second binary within a second region of the memory, and prevents the second binary from accessing the first region of the memory. The first binary implements a kernel configured to control the network interface, while the separate second binary implements a network stack that is restricted to communicate only with an identified set of trusted servers.

PROCESSOR WITH NETWORK STACK DOMAIN AND SYSTEM DOMAIN USING SEPARATE MEMORY REGIONS
20230214535 · 2023-07-06 ·

The disclosed technology is generally directed to network security for processors. In one example of the technology, a computing device includes: a processor, a memory, and a network interface. The computing device executes a first binary within a first region of the memory, executes a separate second binary within a second region of the memory, and prevents the second binary from accessing the first region of the memory. The first binary implements a kernel configured to control the network interface, while the separate second binary implements a network stack that is restricted to communicate only with an identified set of trusted servers.

Secure processor and a program for a secure processor
11550962 · 2023-01-10 · ·

The instruction code including an instruction code stored in the area where the encrypted instruction code is stored in a non-rewritable format is authenticated using a specific key which is specific to the core where the instruction code is executed or an authenticated key by a specific key to perform an encryption processing for the input and output data between the core and the outside.

Secure processor and a program for a secure processor
11550962 · 2023-01-10 · ·

The instruction code including an instruction code stored in the area where the encrypted instruction code is stored in a non-rewritable format is authenticated using a specific key which is specific to the core where the instruction code is executed or an authenticated key by a specific key to perform an encryption processing for the input and output data between the core and the outside.

Devices, methods and systems to augment the security environment of internet-capable consumer devices

The application discloses an electronic operating device (100) arranged to protect communication between a consumer application (125) and a network-connected consumer device (300). The operating device protects a command message by signing the command message with a private key obtained from a key storage of the operating device (optionally also encrypting the command message with an encryption key), and sends the protected command message to the network controller (200). The network controller performs the verification of the signature of the command message such that legacy consumer devices without cryptographic capability can be used. The signature ensures that only authorised devices (100) can send commands to the consumer device (300).

Confirmation system and confirmation method

A trusted application (TA) operates on a trusted execution environment (TEE) and generates a screen. Further, the TA transmits certification information for certifying validity of the TA to a verification device. The verification device verifies whether the TA is valid on the basis of the certification information. Further, the verification device authenticates a display device when the validity of the TA is certified and when the verification device is capable of confirming the facts that a picture is being output and that a device outputting the picture is the display device. Further, the verification device outputs a random number code when the display device is authenticated. Further, the verification device transmits the random number code to the display device when the display device is authenticated. Further, the display device receives the random number code from the verification device and displays the same.