Disclosed herein is application specific integrated circuit (ASIC) redesign for security and analysis testing tool, which includes hardware description language code with on-chip security circuitry for detecting and mitigating hardware Trojan horses (HTHs) in an ASIC chip. The testing tool is used between a design stage of the ASIC chip and a synthesis phase of production of the ASIC chip to add test circuitry to the ASIC chip in order to facilitate testing and protecting of the ASIC chip from the HTHs long after production. The test circuitry facilitates search for HTHs, HTH triggering events, and changes made to the ASIC if the HTH has been activated.

Disclosed herein is application specific integrated circuit (ASIC) redesign for security and analysis testing tool, which includes hardware description language code with on-chip security circuitry for detecting and mitigating hardware Trojan horses (HTHs) in an ASIC chip. The testing tool is used between a design stage of the ASIC chip and a synthesis phase of production of the ASIC chip to add test circuitry to the ASIC chip in order to facilitate testing and protecting of the ASIC chip from the HTHs long after production. The test circuitry facilitates search for HTHs, HTH triggering events, and changes made to the ASIC if the HTH has been activated.

Technologies for secure I/O data transfer include a computing device having a processor and an accelerator. Each of the processor and the accelerator includes a memory encryption engine. The computing device configures both memory encryption engines with a shared encryption key and transfers encrypted data from a source component to a destination component via an I/O link. The source may be processor and the destination may be the accelerator or vice versa. The computing device may perform a cryptographic operation with one of the memory encryption engines and bypass the other memory encryption engine. The computing device may read encrypted data from a memory of the source, bypass the source memory encryption engine, and transfer the encrypted data to the destination. The destination may receive encrypted data, bypass the destination memory encryption engine, and store the encrypted data in a memory of the destination. Other embodiments are described and claimed.

Technologies for secure I/O data transfer include a computing device having a processor and an accelerator. Each of the processor and the accelerator includes a memory encryption engine. The computing device configures both memory encryption engines with a shared encryption key and transfers encrypted data from a source component to a destination component via an I/O link. The source may be processor and the destination may be the accelerator or vice versa. The computing device may perform a cryptographic operation with one of the memory encryption engines and bypass the other memory encryption engine. The computing device may read encrypted data from a memory of the source, bypass the source memory encryption engine, and transfer the encrypted data to the destination. The destination may receive encrypted data, bypass the destination memory encryption engine, and store the encrypted data in a memory of the destination. Other embodiments are described and claimed.

Access control request parameter interleaving may be implemented that supports user-configurable and host-configurable processing stages. A request may be received and evaluated to determine whether user-configured interleaving, host-configured interleaving, or both user-interleaving and host-interleaving are applied. For applied interleaving, two different portions of a request parameter may be swapped.

Access control request parameter interleaving may be implemented that supports user-configurable and host-configurable processing stages. A request may be received and evaluated to determine whether user-configured interleaving, host-configured interleaving, or both user-interleaving and host-interleaving are applied. For applied interleaving, two different portions of a request parameter may be swapped.

Systems, devices, and methods for generating a unique fingerprint are described herein. For example, an example integrated circuit (IC) chip includes a physically unclonable function (PUF) and an auxiliary circuit. The PUF is a hybrid Boolean network. Additionally, the auxiliary circuit is configured to receive a transient response enable signal.

Systems, devices, and methods for generating a unique fingerprint are described herein. For example, an example integrated circuit (IC) chip includes a physically unclonable function (PUF) and an auxiliary circuit. The PUF is a hybrid Boolean network. Additionally, the auxiliary circuit is configured to receive a transient response enable signal.

In some examples, an apparatus can include a memory resource and hardware logic to analyze a plurality of configuration settings associated with a non-volatile storage bit array controlling access to a hardware logic device. In response to detecting an inconsistency in the configuration settings during analysis, the hardware logic device can be placed in a most secure mode to resist a security threat.

In some examples, an apparatus can include a memory resource and hardware logic to analyze a plurality of configuration settings associated with a non-volatile storage bit array controlling access to a hardware logic device. In response to detecting an inconsistency in the configuration settings during analysis, the hardware logic device can be placed in a most secure mode to resist a security threat.