An integrated circuit including an input terminal and an output terminal, signal generator circuitry that generates a pseudo-random digital signal provided at the output terminal, and comparator circuitry that compares an input signal received via the input terminal with the pseudo-random digital signal for providing a tamper detection signal indicative thereof. The signal generator circuitry may be a pseudo-random binary sequence generator or may be a linear-feedback shift register with software triggered reloading. The comparator circuitry may include a Boolean logic exclusive-OR gate for comparing the output and input signals. A method of detecting tampering including generating and providing a pseudo-random digital signal at an output terminal and comparing an input signal received via an input terminal with the pseudo-random digital signal for providing a tamper detection signal indicative thereof.

The present invention provides a system for detecting access to a pre-defined area on a Printed Circuit Board, wherein the system comprises: the Printed Circuit Board comprising, on at least one of its external surfaces, at least one pre-defined area comprising electrical components, a potting material arranged over at least the pre-defined area, wherein the potting material comprises a first layer of transparent material configured to allow light to pass through, and a second layer of opaque material arranged so that completely blocks light towards the first layer, wherein the first layer is arranged between the Printed Circuit Board and the second layer and extends at least over the pre-defined area, and at least one photo-sensor arranged within the first layer of transparent material and configured to generate a tamper signal upon detection of light in the first layer.

An integrated circuit, comprising: a volatile memory module configured to store a cryptographic key; a capacitor array for providing power to the volatile memory module; and a power switching logic arranged to connect and disconnect the memory module from the capacitor array, the power switching logic being configured to operate in at least one of a first operating mode and a second operating mode, wherein, when the power switching logic operates in the first operating mode, the power switching logic is configured to disconnect the capacitor array from the volatile memory module in response to detecting a change of state of a break line, and, when the power switching logic operates in the second operating mode, the power switching logic is configured to disconnect the capacitor array from the volatile memory module in response to detecting that a voltage at a connection terminal of the integrated circuit exceeds a threshold.

An integrated circuit, comprising: a volatile memory module configured to store a cryptographic key; a capacitor array for providing power to the volatile memory module; and a power switching logic arranged to connect and disconnect the memory module from the capacitor array, the power switching logic being configured to operate in at least one of a first operating mode and a second operating mode, wherein, when the power switching logic operates in the first operating mode, the power switching logic is configured to disconnect the capacitor array from the volatile memory module in response to detecting a change of state of a break line, and, when the power switching logic operates in the second operating mode, the power switching logic is configured to disconnect the capacitor array from the volatile memory module in response to detecting that a voltage at a connection terminal of the integrated circuit exceeds a threshold.

Mobile devices executing applications may be tested for networking issues by utilizing a test network having proxy access devices placed at different physical locations. Devices may be stored in a secure enclosure that includes a host device. The enclosure includes access controls to prevent unauthorized removal of devices or access to stored data. If an unauthorized access, disconnection from the host device, or disconnection of a device from a power source is detected, devices may be placed into a locked state or data on the devices may be deleted. The enclosure may also include a control device for testing the exchange of Bluetooth data by the devices. The enclosure may also include conductive members placed on the touch sensors of devices for providing simulated touch input to the touch sensors by changing the capacitance of adjacent regions of the touch sensors.

Mobile devices executing applications may be tested for networking issues by utilizing a test network having proxy access devices placed at different physical locations. Devices may be stored in a secure enclosure that includes a host device. The enclosure includes access controls to prevent unauthorized removal of devices or access to stored data. If an unauthorized access, disconnection from the host device, or disconnection of a device from a power source is detected, devices may be placed into a locked state or data on the devices may be deleted. The enclosure may also include a control device for testing the exchange of Bluetooth data by the devices. The enclosure may also include conductive members placed on the touch sensors of devices for providing simulated touch input to the touch sensors by changing the capacitance of adjacent regions of the touch sensors.

An analog tamper-detection apparatus (ATAMP) for onboard analysis of a target device includes a plurality of antennas, each antenna of the plurality of antennas disposed within the target device and being electrically isolated from components of the target device. The ATAMP device further includes radio frequency (RF) front-end (RFFE) transmitter circuitry coupled to the plurality of antennas, the RFFE transmitter circuitry configured to illuminate the target device with a plurality of electromagnetic signals emitted via the plurality of antennas, to generate a plurality of mixed RF signals. The ATAMP device further includes RFFE receiver circuitry configured to receive emissions from the target device based on the mixed RF signals, and processing circuitry configured to perform subsequent analysis and evaluation of the target device based on the received emissions. The processing circuitry further generates a notification of the subsequent analysis and evaluation.

A program execution device capable of protecting a program against unauthorized analysis and alteration is provided. The program execution device includes an execution unit, a first protection unit, and a second protection unit. The execution unit executes a first program and a second program, and is connected with an external device that is capable of controlling the execution. The first protection unit disconnects the execution unit from the external device while the execution unit is executing the first program. The second protection unit protects the first program while the execution unit is executing the second program.

A program execution device capable of protecting a program against unauthorized analysis and alteration is provided. The program execution device includes an execution unit, a first protection unit, and a second protection unit. The execution unit executes a first program and a second program, and is connected with an external device that is capable of controlling the execution. The first protection unit disconnects the execution unit from the external device while the execution unit is executing the first program. The second protection unit protects the first program while the execution unit is executing the second program.

The embodiments herein are directed to technologies for backside security meshes of semiconductor packages. One package includes a substrate having a first interconnect terminal of a first type and a second interconnect terminal of a second type. The package also includes a first security mesh structure disposed on a first side of an integrated circuit die and a conductive path coupled between the first interconnect terminal and the second interconnect terminal. The first security mesh structure is coupled to the first interconnect terminal and the second interconnect terminal being coupled to a terminal on a second side of the integrated circuit die.