Systems and methods for assembling and developing a System-on-a-chip (SoC) by using templates and designer input data are described. One of the methods includes receiving a request for generating a design of the SoC. In response to the request, a template database is accessed to provide templates of a plurality of designs of systems-on-chips (SoCs). Each of the templates is for a technology application. The method includes receiving a selection of one of the templates. The one of the templates represents components of the SoC. The method also includes receiving a configuration file including configuration data input for the components of the SoC. The method includes compiling the configuration file and a definition file for the SoC to generate design files for the SoC.

Methods of encoding and decoding are described which use a variable number of instruction words to encode instructions from an instruction set, such that different instructions within the instruction set may be encoded using different numbers of instruction words. To encode an instruction, the bits within the instruction are reordered and formed into instruction words based upon their variance as determined using empirical or simulation data. The bits in the instruction words are compared to corresponding predicted values and some or all of the instruction words that match the predicted values are omitted from the encoded instruction.

A method to translate a nervous system model into Hardware Description Language (HDL) is presented here. The nervous system model is that produced from the Nervous System Modeling Tool, patent application Ser. No. 15/660,858, and the HDL translation downloads into either a Field Programmable Gate Array (FPGA) chip or an Application-Specific Integrated Circuit (ASIC) architecture. The method supports the neurobiological realism of Ser. No. 15/660,858 and adds massive parallelism operating at adjustable microchip speeds. A neurobiologically realistic nervous system embedded on a microchip achieves the goal of neuromorphic computing and thus embodies a nervous system on a chip. The potential applications are extensive and cover the range of robotics, big data analysis, medical diagnostics and remediation, self-learning systems, and artificially intelligent applications such as intelligent assistants. Intelligent assistants can be applied to the fields of language and technology exposition, the Internet of Things (IOT) and security.

A method to translate a nervous system model into Hardware Description Language (HDL) is presented here. The nervous system model is that produced from the Nervous System Modeling Tool, patent application Ser. No. 15/660,858, and the HDL translation downloads into either a Field Programmable Gate Array (FPGA) chip or an Application-Specific Integrated Circuit (ASIC) architecture. The method supports the neurobiological realism of Ser. No. 15/660,858 and adds massive parallelism operating at adjustable microchip speeds. A neurobiologically realistic nervous system embedded on a microchip achieves the goal of neuromorphic computing and thus embodies a nervous system on a chip. The potential applications are extensive and cover the range of robotics, big data analysis, medical diagnostics and remediation, self-learning systems, and artificially intelligent applications such as intelligent assistants. Intelligent assistants can be applied to the fields of language and technology exposition, the Internet of Things (IOT) and security.

An analog circuit netlist translation system is disclosed. The analog circuit netlist translation system comprises a model translation module configured to receive an analog circuit netlist; and transform the analog circuit netlist into a digital model. In some embodiments, the digital model comprises a set of zero-delay loops. The analog circuit netlist translation system further comprises a translation methodology module configured to determine a set of closed loop values respectively associated with the set of zero-delay loops, in order to eliminate the set of zero-delay loops within the digital model. In some embodiments, the set of closed loop values are determined by the translation methodology module in a single timeslot.

An analog circuit netlist translation system is disclosed. The analog circuit netlist translation system comprises a model translation module configured to receive an analog circuit netlist; and transform the analog circuit netlist into a digital model. In some embodiments, the digital model comprises a set of zero-delay loops. The analog circuit netlist translation system further comprises a translation methodology module configured to determine a set of closed loop values respectively associated with the set of zero-delay loops, in order to eliminate the set of zero-delay loops within the digital model. In some embodiments, the set of closed loop values are determined by the translation methodology module in a single timeslot.

A computer-implemented method is provided for generating device parameters of circuits using a pretrained reinforcement learning (RL) agent composed of a graph neural network (GNN) and a fully connected neural network (FCNN). The method is performed by steps including acquiring inputs with respect to a set of desired specifications or one desired specification of a circuit, device parameters, a fixed topology of the circuit and providing the inputs to the RL agent. The desired circuit description includes a graph modeling the topology of the circuit and device parameters of the circuit, and the desired specifications include gain, bandwidth, phase margin, power consumption, output power and power efficiency. The pretrained RL agent performs steps including transmitting an action selected from a set of actions to an environment module, updating the device parameters of the circuit according to the selected action using a data processor of the environment module, obtaining a current specification of the circuit by simulating a netlist of the circuit, acquiring a reward from the environment module, and generating the updated device parameters of the circuit.

A computer-implemented method is provided for generating device parameters of circuits using a pretrained reinforcement learning (RL) agent composed of a graph neural network (GNN) and a fully connected neural network (FCNN). The method is performed by steps including acquiring inputs with respect to a set of desired specifications or one desired specification of a circuit, device parameters, a fixed topology of the circuit and providing the inputs to the RL agent. The desired circuit description includes a graph modeling the topology of the circuit and device parameters of the circuit, and the desired specifications include gain, bandwidth, phase margin, power consumption, output power and power efficiency. The pretrained RL agent performs steps including transmitting an action selected from a set of actions to an environment module, updating the device parameters of the circuit according to the selected action using a data processor of the environment module, obtaining a current specification of the circuit by simulating a netlist of the circuit, acquiring a reward from the environment module, and generating the updated device parameters of the circuit.

This disclosure provides a method to realize a hardware device, in particular a hardware device configured on a FPGA or manufactured as an ASIC, configured to meet maximum performances achievable by a certain algorithm defined by a high-level software code. The method is based on the steps of translating of the high-level software code into a corresponding low-level software code defining low-level operation, for executing the same operations defined by the high-level software code; then on estimating of certain parameters to calculate a peak performance value P and memory transfer performance Pm of the hardware device; finally, on realizing the hardware device with hardware resources having performance within the peak performance value P and memory transfer performance Pm.

This disclosure provides a method to realize a hardware device, in particular a hardware device configured on a FPGA or manufactured as an ASIC, configured to meet maximum performances achievable by a certain algorithm defined by a high-level software code. The method is based on the steps of translating of the high-level software code into a corresponding low-level software code defining low-level operation, for executing the same operations defined by the high-level software code; then on estimating of certain parameters to calculate a peak performance value P and memory transfer performance Pm of the hardware device; finally, on realizing the hardware device with hardware resources having performance within the peak performance value P and memory transfer performance Pm.