A method (of reducing errors in a migration a first netlist to a second netlist, the first and second netlists representing corresponding first and second implementations of a circuit design under corresponding first and second semiconductor process technology (SPT) nodes, at least the second netlist being stored on a non-transitory computer-readable medium), the method including: inspecting a timing constraint list for addition candidates, the timing constraint list corresponding to an initial netlist which represents the second implementation; relative to a logic equivalence check (LEC) context, increasing a number of comparison points based on the addition candidates, resulting in first version of the second netlist; performing a LEC between the first netlist and the first version of the second netlist, thereby identifying migration errors; and revising the first version of the second netlist to reduce the migration errors, thereby resulting in a second version of the second netlist.

A method (of reducing errors in a migration a first netlist to a second netlist, the first and second netlists representing corresponding first and second implementations of a circuit design under corresponding first and second semiconductor process technology (SPT) nodes, at least the second netlist being stored on a non-transitory computer-readable medium), the method including: inspecting a timing constraint list for addition candidates, the timing constraint list corresponding to an initial netlist which represents the second implementation; relative to a logic equivalence check (LEC) context, increasing a number of comparison points based on the addition candidates, resulting in first version of the second netlist; performing a LEC between the first netlist and the first version of the second netlist, thereby identifying migration errors; and revising the first version of the second netlist to reduce the migration errors, thereby resulting in a second version of the second netlist.

Embodiments of the present disclosure provide methods, apparatus, systems, computing devices, computing entities for setting deprocessing parameters used in conducting hardware deprocessing on a hardware. In accordance with one embodiment, a method is provided that includes: receiving sample images using different E-beam voltages, wherein each image is captured from a backside of the hardware using a different E-beam voltage; generating thickness-based contour maps, wherein each map is generated for an image and includes contour lines indicating locations having a same thickness of remaining material; generating estimated E-beam penetration depths, wherein each depth is generated for an image and is based at least in part on the E-beam voltage used to capture the image; generating an estimated thickness measurement of the remaining material based at least in part on the contour maps and the penetration depths; and setting the deprocessing parameters based at least in part on the estimated thickness measurement.

Embodiments of the present disclosure provide methods, apparatus, systems, computing devices, computing entities for setting deprocessing parameters used in conducting hardware deprocessing on a hardware. In accordance with one embodiment, a method is provided that includes: receiving sample images using different E-beam voltages, wherein each image is captured from a backside of the hardware using a different E-beam voltage; generating thickness-based contour maps, wherein each map is generated for an image and includes contour lines indicating locations having a same thickness of remaining material; generating estimated E-beam penetration depths, wherein each depth is generated for an image and is based at least in part on the E-beam voltage used to capture the image; generating an estimated thickness measurement of the remaining material based at least in part on the contour maps and the penetration depths; and setting the deprocessing parameters based at least in part on the estimated thickness measurement.

Disclosed is a method of operating a system-on-chip automatic design device. The system-on-chip automatic design device includes a first synthesizer and a second synthesizer. The method includes generating a first code, based on information of a first signal and information of a second signal that are used in a first IP (Intellectual Property) block, classifying a first signal code corresponding to the first signal and a second signal code corresponding to the second signal from the first code, synthesizing, through the first synthesizer, a first communication architecture configured to transmit the first signal, based on the classified first signal code, and synthesizing, through the second synthesizer, a second communication architecture configured to transmit the second signal based on the classified second signal code.

A method for realizing an artificial neural network via an electronic integrated circuit (FPGA), wherein artificial neurons grouped into different interlinked layers for the artificial neural network, where a functional description is created for each neuron of the artificial neural network, taking into account a specifiable starting weighting, a synthesis is performed for each neuron based on the associated functional description with the associated specified starting weighting, a network list is determined as the synthesis result, in which at least a base element and a starting configuration belonging to the base element are stored for each neuron, a base element is formed as a lookup table (LUT) unit and an associated dynamic configuration cell, in which a current configuration for the LUT unit or the base element is stored, and where the network list is implemented as a starting configuration of the artificial neural network in the electronic integrated circuit.

A method for realizing an artificial neural network via an electronic integrated circuit (FPGA), wherein artificial neurons grouped into different interlinked layers for the artificial neural network, where a functional description is created for each neuron of the artificial neural network, taking into account a specifiable starting weighting, a synthesis is performed for each neuron based on the associated functional description with the associated specified starting weighting, a network list is determined as the synthesis result, in which at least a base element and a starting configuration belonging to the base element are stored for each neuron, a base element is formed as a lookup table (LUT) unit and an associated dynamic configuration cell, in which a current configuration for the LUT unit or the base element is stored, and where the network list is implemented as a starting configuration of the artificial neural network in the electronic integrated circuit.

A hardware design for a main data transformation component is verified. The main data transformation component is representable as a hierarchical set of data transformation components which includes (i) a plurality of leaf data transformation components which do not have children, and (ii) one or more parent data transformation components which each comprise one or more child data transformation components. For each of the plurality of leaf data transformation components, it is verified that an instantiation of the hardware design for the leaf data transformation component generates an expected output transaction in response to each of a plurality of test input transactions. For each of the one or more parent data transformation components, it is formally verified, using a formal verification tool, that an instantiation of an abstracted hardware design for the parent data transformation component generates an expected output transaction in response to each of a plurality of test input transactions. The abstracted hardware design for the parent data transformation component represents each of the one or more child data transformation components of the parent data transformation component with a corresponding abstracted component that for a specific input transaction to the child data transformation component is configured to produce a specific output transaction with a causal deterministic relationship to the specific input transaction.

Methods and systems for verifying, via formal verification, a hardware design for a data transformation pipeline comprising one or more data transformation elements that perform a data transformation on one or more inputs, wherein the formal verification is performed under conditions that simplify the data transformations calculations that the formal verification tool has to perform. In one embodiment the hardware design for the data transformation pipeline is verified by formally verifying that the output of an instantiation of the hardware design produces the same output as an instantiation of a hardware design for another data transformation pipeline for a predetermined set of transactions under a constraint that substantially equivalent data transformation elements between the data transformation pipelines produce the same output(s) in response to the same input(s).

A Register Transfer Level (RTL) representation is recovered from a netlist representing an integrated circuit (IC). The netlist is converted to a graph comprising nodes belonging to a set of node types and edges connecting the nodes. The set of node types includes an instance node type representing an electronic component and a wire node type representing signal transfer between components. The graph is converted to a standardized graph by replacing subgraphs of the graph with standardized subgraphs. An RTL representation of the standardized graph is generated by operations including building signal declarations in a hardware description language (HDL) from the wire nodes of the standardized graph and building signal assignments in the HDL from instance nodes of the standardized graph.