Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving a netlist associated with an electronic design and performing genetic optimization on a portion of the netlist to identify and place one or more capacitors on a printed circuit board to minimize an impedance associated with a power plane. Embodiments may further include displaying, at a graphical user interface, a placement of the one or more capacitors, wherein the placement is based upon, at least in part, the performing.

Examples provide a method of virtualizing a hardware accelerator in a virtualized computing system. The virtualized computing system includes a hypervisor supporting execution of a plurality of virtual machines (VMs). The method includes: receiving a plurality of sub-programs at a compiler in the hypervisor from a plurality of compilers in the respective plurality of VMs, each of the sub-programs including a hardware-description language (HDL) description; combining, at the compiler in the hypervisor, the plurality of sub-programs into a monolithic program; generating, by the compiler in the hypervisor, a circuit implementation for the monolithic program, the circuit implementation including a plurality of sub-circuits for the respective plurality of sub-programs; and loading, by the compiler in the hypervisor, the circuit implementation to a programmable device of the hardware accelerator.

Examples provide a method of virtualizing a hardware accelerator in a virtualized computing system. The virtualized computing system includes a hypervisor supporting execution of a plurality of virtual machines (VMs). The method includes: receiving a plurality of sub-programs at a compiler in the hypervisor from a plurality of compilers in the respective plurality of VMs, each of the sub-programs including a hardware-description language (HDL) description; combining, at the compiler in the hypervisor, the plurality of sub-programs into a monolithic program; generating, by the compiler in the hypervisor, a circuit implementation for the monolithic program, the circuit implementation including a plurality of sub-circuits for the respective plurality of sub-programs; and loading, by the compiler in the hypervisor, the circuit implementation to a programmable device of the hardware accelerator.

A method comprises creating an electronic module design having a plurality of electronic components and defining a model of functional behavior of a subset of the plurality of electronic components, the subset of the plurality of electronic components excluding a first electronic component. Functional behavior of the first electronic component is defined in a user-defined functional design intent file based on a first template, and a power behavior of the first electronic component is defined in a user-defined power design intent file based on a second template. A simulation file is generated based on the model of functional behavior and based on the functional behavior and the power behavior of the first electronic component. The simulation file is run to simulate operation of the electronic module design. A performance status is determined of the electronic module design in response to running the simulation file.

A method comprises creating an electronic module design having a plurality of electronic components and defining a model of functional behavior of a subset of the plurality of electronic components, the subset of the plurality of electronic components excluding a first electronic component. Functional behavior of the first electronic component is defined in a user-defined functional design intent file based on a first template, and a power behavior of the first electronic component is defined in a user-defined power design intent file based on a second template. A simulation file is generated based on the model of functional behavior and based on the functional behavior and the power behavior of the first electronic component. The simulation file is run to simulate operation of the electronic module design. A performance status is determined of the electronic module design in response to running the simulation file.

An integrated circuit post-layout simulation method and device, an electronic device and a storage medium are provided and belong to the technical field of semiconductors. The integrated circuit post-layout simulation method includes: acquiring a pre-layout simulation netlist of a to-be-simulated circuit; acquiring a first parasitic netlist of a target sub-element in the to-be-simulated circuit; acquiring a simulation netlist of the to-be-simulated circuit using the first parasitic netlist and the pre-layout simulation netlist; and simulating the simulation netlist.

An integrated circuit post-layout simulation method and device, an electronic device and a storage medium are provided and belong to the technical field of semiconductors. The integrated circuit post-layout simulation method includes: acquiring a pre-layout simulation netlist of a to-be-simulated circuit; acquiring a first parasitic netlist of a target sub-element in the to-be-simulated circuit; acquiring a simulation netlist of the to-be-simulated circuit using the first parasitic netlist and the pre-layout simulation netlist; and simulating the simulation netlist.

Methods and systems for verifying a hardware design for a multi-stage component configured to receive input data and generate output data by processing the input data at each of a plurality of successive stages wherein each stage is independently enabled is stall independent. For each stage from the second stage to the last stage: a relevant portion of the output data of an instantiation of the hardware design is verified as the same if the instantiation is in the same state when that stage is enabled in a cycle by any set of inputs and any subsequent stages are enabled in subsequent cycles by a first minimal sequence of inputs. The relevant portion of the output data of the hardware design is verified as the same if the instantiation is in the same state (i) when that stage is enabled in a cycle and any subsequent stages are enabled in subsequent cycles by a second minimal sequence of inputs and (ii) when that stage is stalled, then that stage is enabled in the next cycle and the subsequent stages are enabled in subsequent cycles by the second minimal sequence of inputs.

Methods and systems for verifying a hardware design for a multi-stage component configured to receive input data and generate output data by processing the input data at each of a plurality of successive stages wherein each stage is independently enabled is stall independent. For each stage from the second stage to the last stage: a relevant portion of the output data of an instantiation of the hardware design is verified as the same if the instantiation is in the same state when that stage is enabled in a cycle by any set of inputs and any subsequent stages are enabled in subsequent cycles by a first minimal sequence of inputs. The relevant portion of the output data of the hardware design is verified as the same if the instantiation is in the same state (i) when that stage is enabled in a cycle and any subsequent stages are enabled in subsequent cycles by a second minimal sequence of inputs and (ii) when that stage is stalled, then that stage is enabled in the next cycle and the subsequent stages are enabled in subsequent cycles by the second minimal sequence of inputs.

An integrated circuit including a multiplier-accumulator execution pipeline including a plurality of multiplier-accumulator circuits to, in operation, perform multiply and accumulate operations, wherein each multiplier-accumulator circuit includes: (i) a multiplier to multiply first input data, having a first floating point data format, by a filter weight data, having the first floating point data format, and generate and output a product data having a second floating point data format, and (ii) an accumulator, coupled to the multiplier of the associated MAC circuit, to add second input data and the product data output by the associated multiplier to generate sum data. The plurality of multiplier-accumulator circuits of the multiplier-accumulator execution pipeline may be connected in series and, in operation, perform a plurality of concatenated multiply and accumulate operations.