A mixed-signal integrated circuit includes an analog circuit comprising at least one digital block embedded in the analog circuit, the at least one digital block comprising a plurality of functional bits and a plurality of configuration bits, the plurality of functional bits providing for a functionality of the analog circuit according to a designed functionality and the plurality of configuration bits being usable for configuring a plurality of operational modes of the analog circuit; and a digital circuit comprising a scan chain configured to scan at least part of the functional bits of the digital block embedded in the analog circuit with respect to the designed functionality, wherein the scan chain is further configured to set at least part of the configuration bits of the digital block embedded in the analog circuit according to a selected operational mode of the plurality of operational modes of the analog circuit.

A system and method may determine the operating parameters, such as voltages, of MOS transistors within a circuit design by testing or simulation, for example and may identify a MOS transistor operating with its drain voltage higher than its gate voltage in the circuit. The design system and method may substitute a smaller transistor, having a high-k dielectric layer, for the original transistor in the circuit design.

A storage unit stores statistical information including an amount of resource consumption and performance information, which represents a performance, of each piece of hardware of a plurality of types that are candidates for an arrangement destination of a function, an accepting unit accepts inputs of description details of a function in a high-level language corresponding to the hardware of the plurality of types, and a performance requirement that represents a required performance, a performance predicting unit calculates a predicted performance, and a predicted amount of resource consumption, using the description details and a predetermined algorithm for each piece of hardware; and a device selecting unit selects, as an arrangement destination, hardware with the calculated predicted performance and the performance information satisfying the performance requirement and a total value of the predicted amount of resource consumption and the amount of resource consumption being equal to or smaller than a resource capacity.

A storage unit stores statistical information including an amount of resource consumption and performance information, which represents a performance, of each piece of hardware of a plurality of types that are candidates for an arrangement destination of a function, an accepting unit accepts inputs of description details of a function in a high-level language corresponding to the hardware of the plurality of types, and a performance requirement that represents a required performance, a performance predicting unit calculates a predicted performance, and a predicted amount of resource consumption, using the description details and a predetermined algorithm for each piece of hardware; and a device selecting unit selects, as an arrangement destination, hardware with the calculated predicted performance and the performance information satisfying the performance requirement and a total value of the predicted amount of resource consumption and the amount of resource consumption being equal to or smaller than a resource capacity.

Some embodiments of the invention relate to generating correction information based on global or regional navigation satellite system (NSS) multiple-frequency signals observed at a network of reference stations, broadcasting the correction information, receiving the correction information at one or more monitoring stations, estimating ambiguities in the carrier phase of the NSS signals observed at the monitoring station(s) using the correction information received thereat, generating residuals, generating post-broadcast integrity information based thereon, and broadcasting the post-broadcast integrity information. Other embodiments relate to receiving and processing correction information and post-broadcast integrity information at NSS receivers or at devices which may have no NSS receiver, as well as to systems, NSS receivers, devices which may have no NSS receiver, processing centers, and computer programs. Some embodiments may for example be used for safety-critical applications such as highly-automated driving and autonomous driving.

Some embodiments of the invention relate to generating correction information based on global or regional navigation satellite system (NSS) multiple-frequency signals observed at a network of reference stations, broadcasting the correction information, receiving the correction information at one or more monitoring stations, estimating ambiguities in the carrier phase of the NSS signals observed at the monitoring station(s) using the correction information received thereat, generating residuals, generating post-broadcast integrity information based thereon, and broadcasting the post-broadcast integrity information. Other embodiments relate to receiving and processing correction information and post-broadcast integrity information at NSS receivers or at devices which may have no NSS receiver, as well as to systems, NSS receivers, devices which may have no NSS receiver, processing centers, and computer programs. Some embodiments may for example be used for safety-critical applications such as highly-automated driving and autonomous driving.

Systems and methods for obfuscating a circuit design are described. One of the methods includes receiving the circuit design from a user computing device. The circuit design includes a plurality of circuit components. The method further includes obfuscating each of the circuit components by transforming layout features associated with the circuit design into a generic layout feature representation. The generic layout feature representation excludes scaled representations of the layout features. The method also includes generating a visual representation of the obfuscated designs. Each of the obfuscated designs has an input port and an output port. The method further includes enabling placement of the obfuscated designs and routing between the input ports and the output ports of the obfuscated designs. The method includes generating an obfuscated integrated circuit design having a master input port, a master output port, the obfuscated designs, and the routing between the obfuscated designs.

An emulator is configured with a circuit design model for a circuit design comprising a processor and is running with an operating system. Data are transferred from a computer to a memory in the emulator through a design-independent interface or a transaction-level interface. A software program is then activated in the emulator to enable the data to be accessed by the operating system without rebooting the emulator.

Disclosed herein are techniques for analyzing control-flow integrity based on functional line-of-code behavior and relation models. Techniques include receiving data based on runtime operations of a controller; constructing a line-of-code behavior and relation model representing execution of functions on the controller based on the received data; constructing, based on the line-of-code behavioral and relation model, a dynamic control flow integrity model configured for the controller to enforce in real-time; and deploying the dynamic control flow integrity model to the controller.

An exemplary method for generating a test vector to activate a Trojan triggering condition includes the operations of obtaining a design graph representation of an electronic circuit; constructing a satisfiability graph from the design graph representation, wherein the satisfiability graph includes a set of vertices representing rare signals of the electronic circuit and satisfiability connections between the vertices; finding a plurality of maximal satisfiable cliques in the satisfiability graph, wherein a maximal satisfiable clique corresponds to a triggering condition for a payload of the electronic circuit; generating a test vector for each of the maximal satisfiable cliques; and performing a test for the presence of a hardware Trojan circuit in the electronic circuit using the generated test vectors as input signals.