A computer-implemented method of designing at least a portion of an electronic circuit schematic is described herein. The method comprises receiving requirements for an electronic circuit or at least a portion of an electronic circuit, creating a set of variables and constraints based on the requirements for the electronic circuit, wherein the constraints limit the possible value that may be assigned to the variables, assigning values to the variables using a solver such that the values of the variables satisfy the constraints, and outputting at least a portion of a designed electronic circuit schematic or circuit schematic specification that meets the requirements for the electronic circuit based on the assigned values of the variables.

A computer-implemented method of designing at least a portion of an electronic circuit schematic is described herein. The method comprises receiving requirements for an electronic circuit or at least a portion of an electronic circuit, creating a set of variables and constraints based on the requirements for the electronic circuit, wherein the constraints limit the possible value that may be assigned to the variables, assigning values to the variables using a solver such that the values of the variables satisfy the constraints, and outputting at least a portion of a designed electronic circuit schematic or circuit schematic specification that meets the requirements for the electronic circuit based on the assigned values of the variables.

A power electronic circuit fault diagnosis method based on Extremely randomized trees (ET) and Stack Sparse auto-encoder (SSAE) algorithm includes the following. First, collect the fault signal and extract fault features. Then, reduce the dimensionality of fault features by calculating the importance value of all features using ET algorithm. A proportion of the features to be eliminated is determined, and a new feature set is obtained according the value of importance. Further extraction of fault features is carried by using SSAE algorithm, and hidden layer features of the last sparse auto-encoder are obtained as fault features after dimensionality reduction. Finally, the fault samples in a training set and a test set are input to the classifier for training to obtain a trained classifier. And mode identification, wherein the fault of the power electronic circuit is identified and located by the training classifier.

A power electronic circuit fault diagnosis method based on Extremely randomized trees (ET) and Stack Sparse auto-encoder (SSAE) algorithm includes the following. First, collect the fault signal and extract fault features. Then, reduce the dimensionality of fault features by calculating the importance value of all features using ET algorithm. A proportion of the features to be eliminated is determined, and a new feature set is obtained according the value of importance. Further extraction of fault features is carried by using SSAE algorithm, and hidden layer features of the last sparse auto-encoder are obtained as fault features after dimensionality reduction. Finally, the fault samples in a training set and a test set are input to the classifier for training to obtain a trained classifier. And mode identification, wherein the fault of the power electronic circuit is identified and located by the training classifier.

A directed acyclic graph (DAG) and an extended regular expression (ERE) may be received. A circuit design may be generated based on the DAG. A cover property may be generated based on the ERE. The circuit design may be simulated. A first result may be determined based on whether the cover property is satisfied during the simulating the circuit design. It may be determined whether the ERE matches a path in the DAG based on the first result.

A detection unit (231) detects, based on synthesis result data obtained by logic synthesis on design data of a target circuit, a predicted place where a glitch is predicted to occur in the target circuit. An insertion unit (232) inserts a glitch removal circuit in an output side of the predicted place by making a change to at least one of the synthesis result data and the design data.

A simulation system and a method thereof are disclosed. In the simulation system, a system power transmission model, and analog current time-domain model and digital current time-domain model are connected to obtain power noise generated after a supply current is obtained; jitter time-domain information of each interface connection circuit model under the power noise is obtained based on transmission of a clock signal outputted from a phase lock loop, by a simulation program; next, a voltage step response of a voltage measurement point when a clock terminal of each interface connection circuit model receives an ideal signal, is simulated by the simulation program to generate a first voltage time-domain model; a system waveform is generated based on the jitter time-domain information of each interface connection circuit model under the power noise, the first voltage time-domain model and data transmission, thereby obtaining an eye diagram and time-domain jitter distribution.

Embodiments include dynamic control of coverage by a verification testbench. Aspects include obtaining a design under test to be verified by the verification testbench and obtaining one or more testcases for execution by the verification testbench on the design under test. Aspects also include obtaining a plurality of triggers corresponding to the design under test, wherein each of the plurality of triggers includes an activation condition, a deactivation condition and a coverage. Aspects further include simulating, by the verification testbench, execution of the one or more testcases by the design under test. Based on detecting the activation condition of one of the plurality of triggers, aspects also include recording, in a coverage database, data specified in the coverage corresponding the one of the plurality of triggers until the deactivation condition is detected.

Disclosed herein are techniques for visualizing and configuring controller function sequences. Techniques include identifying at least one executable code segment associated with a controller; analyzing the at least one executable code segment to determine at least one function and at least one functional relationship associated with the at least one code segment; constructing, a software functionality line-of-code behavior and relation model visually depicting the determined at least one function and at least one functional relationship; displaying the software functionality line-of-code behavior and relation model at a user interface; receiving a first input at the interface; in response to the received first input, animating the line-of-code behavior and relation model to visually depict execution of the at least one executable code segment on the controller; receiving a second input at the interface; and in response to the received second input, animating an update to the line-of-code behavior and relation model.

Disclosed herein are techniques for visualizing and configuring controller function sequences. Techniques include identifying at least one executable code segment associated with a controller; analyzing the at least one executable code segment to determine at least one function and at least one functional relationship associated with the at least one code segment; constructing, a software functionality line-of-code behavior and relation model visually depicting the determined at least one function and at least one functional relationship; displaying the software functionality line-of-code behavior and relation model at a user interface; receiving a first input at the interface; in response to the received first input, animating the line-of-code behavior and relation model to visually depict execution of the at least one executable code segment on the controller; receiving a second input at the interface; and in response to the received second input, animating an update to the line-of-code behavior and relation model.