According to one embodiment, an integrated circuit verification device includes: a condition property information generation unit configured to generate a plurality of condition properties that have information which imposes limitations on circuit operations or input signals, based on condition statements in a code list of a design data file; an exclusion code generation unit configured to generate, from the code list, exclusion code which is proved not to be statically covered, and a first exclusion code list to which the plurality of condition properties are applied; and an exclusion code comparison unit configured to generate a second exclusion code list from a difference between the exclusion code and the first exclusion code list.

The present disclosure provides a satisfiability modulo theory (SMT) modeling system that includes graphical representation circuitry to generate graphical data representing a circuit design; finite state machine (FSM) discovery circuitry to discover, based on a feedback loop of the circuit design, an FSM contained within the graphical data; SMT assertion generation circuitry to generate an SMT assertion set of the FSM, based on the combinatorial and/or sequential logic elements associated with the FSM; and SMT modeling circuitry to determine a behavior of the FSM by applying one or more logical functions to the SMT assertion set.

The present disclosure provides a satisfiability modulo theory (SMT) modeling system that includes graphical representation circuitry to generate graphical data representing a circuit design; finite state machine (FSM) discovery circuitry to discover, based on a feedback loop of the circuit design, an FSM contained within the graphical data; SMT assertion generation circuitry to generate an SMT assertion set of the FSM, based on the combinatorial and/or sequential logic elements associated with the FSM; and SMT modeling circuitry to determine a behavior of the FSM by applying one or more logical functions to the SMT assertion set.

There is a need for more effective and efficient printed circuit board (PCB) design. This need can be addressed by, for example, solutions for performing automated PCB component estimation. In one example, a method includes identifying a plurality of initial component estimations for the PCB; performing a shadow detection segmentation using the plurality of initial component estimations, a non-direct-lighting image, and one or more direct-lighting images to generate a first set of detected PCB components; performing a super-pixel segmentation using the plurality of initial component estimations and the non-direct-lighting-image to generate a second set of detected PCB components; and generating a bill of materials for the PCB based at least in part on the first set of detected PCB components and the second set of detected PCB components.

The present application discloses a verification platform for a system on chip and a verification method thereof, the method comprises: generating, by an Universal Verification Methodology test instance, constrained random parameters and random controls, and storing them to a storage area of a bus function model unit; reading, by a software test instance, the random parameters and the random controls through the central processing unit, and configuring a test of the system on chip; storing execution status information of the software test instance in the storage area; reading, by the Universal Verification Methodology test instance, the execution status information, and adjusting constraint condition for generating random parameters and random controls based on the execution status information to exclude having been tested scenarios, and converting the execution status information into coverage data for coverage analysis.

The present application discloses a verification platform for a system on chip and a verification method thereof, the method comprises: generating, by an Universal Verification Methodology test instance, constrained random parameters and random controls, and storing them to a storage area of a bus function model unit; reading, by a software test instance, the random parameters and the random controls through the central processing unit, and configuring a test of the system on chip; storing execution status information of the software test instance in the storage area; reading, by the Universal Verification Methodology test instance, the execution status information, and adjusting constraint condition for generating random parameters and random controls based on the execution status information to exclude having been tested scenarios, and converting the execution status information into coverage data for coverage analysis.

A method of verifying safety in a circuit design, includes, in part, receiving data representative of the circuit design, identifying a first safety mechanism within the circuit design where the safety mechanism is represented by a first module and has an output port defining a first diagnostic point, identifying a multitude of ports of a second module within the circuit design, determining whether at least one port of the second module is associated with a safety concern, performing a backward path tracing from the first diagnostic point to determine if the port falls within a cone of influence of the first safety mechanism, and establishing that a potential fault appearing at the port is detectable at the first diagnostic point if the port is determined to fall within the cone of influence of the first safety mechanism.

A method of verifying safety in a circuit design, includes, in part, receiving data representative of the circuit design, identifying a first safety mechanism within the circuit design where the safety mechanism is represented by a first module and has an output port defining a first diagnostic point, identifying a multitude of ports of a second module within the circuit design, determining whether at least one port of the second module is associated with a safety concern, performing a backward path tracing from the first diagnostic point to determine if the port falls within a cone of influence of the first safety mechanism, and establishing that a potential fault appearing at the port is detectable at the first diagnostic point if the port is determined to fall within the cone of influence of the first safety mechanism.

A method for determining a metric of a feature on a substrate obtained by a semiconductor manufacturing process involving a lithographic process, the method including: obtaining an image of at least part of the substrate, wherein the image includes at least the feature; determining a contour of the feature from the image; determining a plurality of segments of the contour; determining respective weights for each of the plurality of segments; determining, for each of the segments, an image-related metric; and determining the metric of the feature in dependence on the weights and the calculated image-related metric of each of the segments.

Predicting power usage of a chip may include receiving placement data describing a placement, within the chip, of a plurality of logical components of the chip; providing the placement data as an input to a neural network; and determining, by the neural network, based on the placement data, a predicted power usage of the chip.