An IC is provided. The IC includes an input pin, a controller, a timer, a first memory, a processor, at least one output pin, an output module coupled to the output pin, and a direct memory access (DMA) device coupled between the output module and the first memory. The controller is configured to provide a first control signal in response to a command from the input pin. The timer is configured to periodically provide a trigger signal according to the first control signal. The processor is configured to store first data in the first memory. The DMA device is configured to obtain the first data from the first memory in response to the trigger signal, and transmit the first data to the output module. The output module is configured to provide the first data to the output pin according to a transmission rate.

An IC is provided. The IC includes an input pin, a controller, a timer, a first memory, a processor, at least one output pin, an output module coupled to the output pin, and a direct memory access (DMA) device coupled between the output module and the first memory. The controller is configured to provide a first control signal in response to a command from the input pin. The timer is configured to periodically provide a trigger signal according to the first control signal. The processor is configured to store first data in the first memory. The DMA device is configured to obtain the first data from the first memory in response to the trigger signal, and transmit the first data to the output module. The output module is configured to provide the first data to the output pin according to a transmission rate.

A method, a computing device, and a non-transitory machine-readable medium for modifying cache settings in the array cache are provided. Cache settings are set in an array cache, such that the array cache caches data in an input/output (I/O) stream based on the cache settings. Multiple cache simulators simulate the caching the data from the I/O stream in the array cache using different cache settings in parallel with the array cache. The cache settings in the array cache are replaced with the cache settings from one of the cache simulators based on the determination that the cache simulators increase effectiveness of caching data in the array cache.

A method, a computing device, and a non-transitory machine-readable medium for modifying cache settings in the array cache are provided. Cache settings are set in an array cache, such that the array cache caches data in an input/output (I/O) stream based on the cache settings. Multiple cache simulators simulate the caching the data from the I/O stream in the array cache using different cache settings in parallel with the array cache. The cache settings in the array cache are replaced with the cache settings from one of the cache simulators based on the determination that the cache simulators increase effectiveness of caching data in the array cache.

A method for determining a metric of a feature on a substrate obtained by a semiconductor manufacturing process involving a lithographic process, the method including: obtaining an image of at least part of the substrate, wherein the image includes at least the feature; determining a contour of the feature from the image; determining a plurality of segments of the contour; determining respective weights for each of the plurality of segments; determining, for each of the segments, an image-related metric; and determining the metric of the feature in dependence on the weights and the calculated image-related metric of each of the segments.

This high-level synthesis device, which has a processor and a memory, and generates a hardware description code that describes the configuration of an integrated circuit connected to an external memory, comprises a high-level synthesis code adjustment unit which receives a high-level synthesis code that describes a process to be executed by the integrated circuit and an external memory access variable for exchanging data with the external memory, analyzes the high-level synthesis code, and reconstructs the high-level synthesis code on the basis of the analysis result, wherein the high-level synthesis code adjustment unit includes: a burst access determination unit that analyzes the external memory access variable in the high-level synthesis code, and determines whether burst access to the external memory is possible; and a code reconstructing unit that adds a code for executing burst access to the high-level synthesis code, for the external memory access variable capable of being burst accessed.

A method includes receiving an integrated circuit (IC) design layout including a layout block, where the layout block including first line patterns disposed along a first direction, extending lengths of the first line patterns, connecting portions of the first line patterns disposed within a distance less than a preset value, forming second line patterns disposed outside the layout block parallel to the first line patterns, forming mandrel bar patterns overlapping edges of the layout block, where the mandrel bar patterns oriented along a second direction perpendicular to the first direction, and outputting a pattern layout for mask fabricating, where the pattern layout includes the layout block, the first and second line patterns, and the mandrel bar patterns.

A method includes receiving an integrated circuit (IC) design layout including a layout block, where the layout block including first line patterns disposed along a first direction, extending lengths of the first line patterns, connecting portions of the first line patterns disposed within a distance less than a preset value, forming second line patterns disposed outside the layout block parallel to the first line patterns, forming mandrel bar patterns overlapping edges of the layout block, where the mandrel bar patterns oriented along a second direction perpendicular to the first direction, and outputting a pattern layout for mask fabricating, where the pattern layout includes the layout block, the first and second line patterns, and the mandrel bar patterns.

The present disclosure provides a method of mesh generation for an RTM process, including operations of: obtaining a geometry of a target object; generating a solid mesh of the target object according to the geometry; obtaining material characteristics of the target object; assembling a runner mesh with the solid mesh, wherein the runner mesh has grid dimensions different from those of the solid mesh; determining process parameters of the RTM process; and generating a forecasted result of the RTM process according to the solid mesh, the runner mesh, the process parameters, and the material characteristics. Generating the solid mesh includes operations of: dividing the geometry into modules; generating a first and second modular meshes corresponding to a first and second modules, wherein the second modular mesh abuts the first modular mesh, and the second modular mesh has grid dimensions different from those of the first modular mesh.

Techniques regarding the development and/or analysis of one or more quantum computing programs are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a circuit component, operatively coupled to the processor, that can create a quantum computing program over a period of time. The computer executable components can also comprise a visualization component, operatively coupled to the processor, that can generates a quantum state visualization that depicts a characterization of the quantum computing program over the period of time.