Embodiments disclosed herein describe switching logic in board-level interconnects and in the system-level interconnects that may provide bitwise dynamic routing and switching between corresponding board-level and system-level components. At board-level, a switching ASIC may receive input data through a backplane from an emulation ASIC in a first logic board and route any bit of the input data to any of the emulation ASIC in a second logic board. At system-level, a switching logic board containing a set of switching ASICs may be associated with a logic cluster and may dynamically route data bits from the emulation ASICs in the logic cluster to emulation ASICs to other logic clusters of the emulation system and/or target systems. Additionally, the switching logic board may dynamically route bits from the other logic clusters to the associated logic cluster.

Based on a directive in a control file, a processor pre-routes, within a hierarchical integrated circuit design, a signal through one or more levels of design hierarchy between a signal source at a higher level of the design hierarchy and an entity instance at a lower level of the design hierarchy. The processor processes entity instances in the design hierarchy in a bottom-up manner to insert technology-specific structures into the hierarchical integrated circuit design. During the processing, the processor inserts into a particular entity instance of the design hierarchy a technology-specific structure and connects the technology-specific structure to the signal pre-routed to the particular entity instance by the pre-routing.

Based on a directive in a control file, a processor pre-routes, within a hierarchical integrated circuit design, a signal through one or more levels of design hierarchy between a signal source at a higher level of the design hierarchy and an entity instance at a lower level of the design hierarchy. The processor processes entity instances in the design hierarchy in a bottom-up manner to insert technology-specific structures into the hierarchical integrated circuit design. During the processing, the processor inserts into a particular entity instance of the design hierarchy a technology-specific structure and connects the technology-specific structure to the signal pre-routed to the particular entity instance by the pre-routing.

A physical simulation test method for detecting a position of a ponding goaf in the excavation, which relates to physical detection of mines. This method includes: fabricating an experimental model of a composition similar to that of an excavating tunnel; fabricating a transient transmitting coil and receiving coil; connecting the coil to a wire and placing them in model A; connecting the coil to a transient electromagnetometer; injecting water into a trapezoidal goaf through a pre-buried plastic pipe; after the goaf is filled with water, immediately switching the transient electromagnetometer on to collect data; respectively transferring the coil to models B, C and D, injecting water and switching on the transient electromagnetometer to collect data; statistically analyzing detection and imaging results of the four models; and comparing the detection results with the actual data to determine detection accuracy and correction coefficient.

A physical simulation test method for detecting a position of a ponding goaf in the excavation, which relates to physical detection of mines. This method includes: fabricating an experimental model of a composition similar to that of an excavating tunnel; fabricating a transient transmitting coil and receiving coil; connecting the coil to a wire and placing them in model A; connecting the coil to a transient electromagnetometer; injecting water into a trapezoidal goaf through a pre-buried plastic pipe; after the goaf is filled with water, immediately switching the transient electromagnetometer on to collect data; respectively transferring the coil to models B, C and D, injecting water and switching on the transient electromagnetometer to collect data; statistically analyzing detection and imaging results of the four models; and comparing the detection results with the actual data to determine detection accuracy and correction coefficient.

To predict characteristics of a semiconductor device, a simulation current-voltage curve of the semiconductor device is generated using compact models where each compact model generates simulation result data by performing a simulation based on device data. The simulation result data indicate characteristics of semiconductor devices corresponding to the device data. The compact models respectively corresponding to process data and semiconductor products. Simulation reference points on the simulation current-voltage curve are extracted. Basic training data corresponding to a combination of the simulation reference points and the simulation current-voltage curve are generated. A deep learning model is trained based on the basic training data such that the deep learning model outputs a prediction current-voltage curve. A target prediction current-voltage curve is generated based on the deep learning model and target reference points corresponding to the target semiconductor product. The deep learning model is a generative adversarial network.

To predict characteristics of a semiconductor device, a simulation current-voltage curve of the semiconductor device is generated using compact models where each compact model generates simulation result data by performing a simulation based on device data. The simulation result data indicate characteristics of semiconductor devices corresponding to the device data. The compact models respectively corresponding to process data and semiconductor products. Simulation reference points on the simulation current-voltage curve are extracted. Basic training data corresponding to a combination of the simulation reference points and the simulation current-voltage curve are generated. A deep learning model is trained based on the basic training data such that the deep learning model outputs a prediction current-voltage curve. A target prediction current-voltage curve is generated based on the deep learning model and target reference points corresponding to the target semiconductor product. The deep learning model is a generative adversarial network.

A circuit hardware emulation module is configured to identify oscillating subgraphs of an emulated graph, or to identify state-holding subgraphs of an emulated graph. The emulation module identifies one or more loops within an emulated circuit; generates an acyclic emulation of at least a portion of the emulated circuit, wherein the acyclic emulation is characterized by one or more loop breakers; generates a loop detector emulation of a hardware-based loop detector circuit based at least in part on a quantity of loop breakers n characterizing the acyclic emulation, wherein the loop detector emulation comprises at least one of an oscillation detector or a state-holding detector; and executes the loop detector emulation for a plurality of input values for the emulated circuit to generate an output indicating at least one of an oscillation status or a state-holding status of the emulated circuit.

A system includes a test access port (TAP) configured to provide internal joint test action group (IJTAG) access to one or more test data registry (TDR). The system further includes a plurality of hierarchical electronic components, wherein each hierarchical electronic component includes a de-asserted segment inserted bit (D-SIB) register, an asserted segment inserted bit (A-SIB) register, and a TDR associated with the D-SIB register. Each D-SIB register is configured to prevent access to its associated TDR when a reset signal is asserted and each A-SIB register is configured to provide access to its subsequent A-SIB register or D-SIB register coupled thereto when the reset signal is asserted.

A system includes a test access port (TAP) configured to provide internal joint test action group (IJTAG) access to one or more test data registry (TDR). The system further includes a plurality of hierarchical electronic components, wherein each hierarchical electronic component includes a de-asserted segment inserted bit (D-SIB) register, an asserted segment inserted bit (A-SIB) register, and a TDR associated with the D-SIB register. Each D-SIB register is configured to prevent access to its associated TDR when a reset signal is asserted and each A-SIB register is configured to provide access to its subsequent A-SIB register or D-SIB register coupled thereto when the reset signal is asserted.