A method and apparatus for selecting Si wafer WP based on individual or multiple DFM decks for Si-feed-forward and Si-feed-back analysis are provided. Embodiments include generating markers for a wafer from an individual DFM deck; generating UCF Indexes; determining whether a representative marker corresponding to a UCF is a candidate for WP prediction; extracting markers corresponding to that UCF-Index (UEF data) from a candidate; performing a UCF-Index-based sampling on the extracted UEF data set if a number of markers in the extracted UEF data set is larger than an inspection requirement; adding a location of each marker or group of markers in the extracted UEF data set to a sitelist after the UCF-Index-based sampling; sending the sitelist to a foundry for metrology analysis on sitelist locations; and adding the sitelist locations and corresponding UCF Index and metrology parameters to a design analysis database for analyzing other wafers/UCF Indexes.

Various aspects of the disclosed technology relate to machine learning-based chain diagnosis. Faults are injected into scan chains in a circuit design. Simulations are performed on the fault-injected circuit design to determine test response patterns in response to the test patterns which are captured by the scan chains. Observed failing bit patterns are determined by comparing the unloaded test response patterns with corresponding good-machine test response patterns. Bit-reduction is performed on the observed failing bit patterns to construct training samples. Using the training samples, machine-learning models for faulty scan cell identification are trained. The bit reduction comprises pattern-based bit compression for good scan chains or cycle-based bit compression for the good scan chains. The bit reduction may further comprise bit-filtering. The bit-filtering may comprises keeping only sensitive bits on faulty scan chains for the training samples construction.

Various aspects of the disclosed technology relate to machine learning-based chain diagnosis. Faults are injected into scan chains in a circuit design. Simulations are performed on the fault-injected circuit design to determine test response patterns in response to the test patterns which are captured by the scan chains. Observed failing bit patterns are determined by comparing the unloaded test response patterns with corresponding good-machine test response patterns. Bit-reduction is performed on the observed failing bit patterns to construct training samples. Using the training samples, machine-learning models for faulty scan cell identification are trained. The bit reduction comprises pattern-based bit compression for good scan chains or cycle-based bit compression for the good scan chains. The bit reduction may further comprise bit-filtering. The bit-filtering may comprises keeping only sensitive bits on faulty scan chains for the training samples construction.

A semiconductor device comprises a design under test (DUT), a testing interface, pattern generation circuitry, and pattern checker circuitry. The pattern generation circuitry is connected to the DUT and the testing interface. The pattern generation circuitry is configured to generate a test data sequence and control data based on configuration data received from the testing interface, and communicate the test data sequence and the control data to the DUT. The pattern checker circuitry is connected to the DUT and the testing interface. The pattern checker circuitry is configured to generate a comparison test sequence based on the configuration data received from the testing interface, receive resultant test data sequence and output control data from the DUT, and generate a first error signal based on a comparison of the resultant test data sequence and the comparison test sequence and a comparison of the output control data and the configuration data.

A semiconductor device comprises a design under test (DUT), a testing interface, pattern generation circuitry, and pattern checker circuitry. The pattern generation circuitry is connected to the DUT and the testing interface. The pattern generation circuitry is configured to generate a test data sequence and control data based on configuration data received from the testing interface, and communicate the test data sequence and the control data to the DUT. The pattern checker circuitry is connected to the DUT and the testing interface. The pattern checker circuitry is configured to generate a comparison test sequence based on the configuration data received from the testing interface, receive resultant test data sequence and output control data from the DUT, and generate a first error signal based on a comparison of the resultant test data sequence and the comparison test sequence and a comparison of the output control data and the configuration data.

A simulation apparatus includes a database configured to a set line parameter for a system line configuring a power system; a parameter error detector configured to compare surveyed data measured in the system line and the line parameter to detect error of the line parameter; a system analysis simulator configured to perform a system analysis simulation based on the surveyed data and the line parameter; and a monitor configured to display an error detection result of the line parameter from the parameter error detector and a system analysis simulation result performed in the system analysis simulator.

A testing method of a human-computer combination quality testing system includes steps of: after manufacture, importing relevant CAD models, submitting the CAD models to a digital testing part for being examined; if a product is determined to be unqualified, returning the product for retreatment; if the product is determined to be qualified, submitting the product to a manual testing part for being examined by relevant inspectors; if the product is determined to be qualified by the inspectors, leaving the product as a qualified product; if the product is determined to be unqualified by the inspectors, returning the product for retreatment; then changing the relevant rule with a rule corrector of a system improving part according to a misjudging condition of the digital testing part; describing a corrected rule, which is corrected by the developer, by a rule descriptor; then applying the corrected rule to a system by a rule parser.

Methods and apparatus for performing profile-guided optimization of integrated circuit hardware are provided. Circuit design tools may receive a source code and compile the source code to generate a hardware description. The hardware description may include profiling blocks configured to measure useful information required for optimization. The hardware description may then be simulated to gather profiling data. The circuit design tools may then analyze the gathered profiling data to identify additional opportunities for hardware optimization. The source code may then be modified based on the analysis of the profiling data to produce a smaller and faster hardware that is better suited to the application.

A method for inspecting a group of dies of a wafer, wherein the wafer comprises a group of wafer segments, wherein each wafer segment comprises a die of the group of dies, a molded material that surrounds the die and redistribution layer (RDL) conductors that are coupled to the die and are positioned above the die and the molded material, wherein the method includes the steps of: receiving design information about the RDL conductors of each wafer segment of the group of wafer segments; obtaining, during a setup process, first images of the group of wafer segments; wherein the obtaining of the first images comprises illuminating the group of wafer segments with radiation and detecting radiation scattered or reflected from the group of wafer segments as a result of the illuminating; generating reference information based on the design information about the RDL conductors of one or more wafer segments of the group of wafer segments and at least one first image of the one or more first images; acquiring, during an inspection process, a second image of each wafer segment of the group of wafer segments; and evaluating each wafer segment of the group of wafer segments based on the second image of the wafer segment and the reference information of the wafer segment.

A method for verification of a design of an electronic circuit is provided. The method includes executing test runs of the design. The method further includes increasing a fail counter if the executing of a test run of the test runs failed. The method further includes increasing a pass counter if the executing of the test run of the test runs passed. The method further includes halting the executing of the test runs of the design if the current ratio of the fail counter versus the pass counter exceeds a predetermined threshold.