A method, apparatus, computer device, and storage medium for automatic design of analog circuits based on tree structure. The method includes: setting the maximum height and growth direction of the tree structure; randomly calling the node from the function node library as the parent node; randomly calling the node from the function node library and the port node library as the child according to the growth direction node; if the child node is a terminal node, generating a tree structure; checking the tree structure, if the tree structure satisfies the preset conditions, obtaining the circuit topology and device parameter that conform to the circuit rules; evolving the circuit topology and device parameter to generate an analog circuit. The embodiments achieve the effect of making the tree structure of the designed analog circuit more reasonable.

A system and method are provided to enable non-quantum experts to schematically represent, simulate and quantify the performance of physically realistic photonic quantum circuits. The framework offers the flexibility for users—not necessarily familiar with the fundamentals of quantum mechanics—to create circuits and work with simple inputs and outputs, while the complexities of manipulating high dimensionality quantum Hilbert spaces supporting photonic and physical quantum object states are handled with the use of purpose-built tools. The tools include a user-friendly method for defining classical photonic circuits which may be coupled to physical objects such as qubits, quantum input states, as well as classical and quantum measurement devices. The tools feature classical-to-quantum S-matrix conversion, quantum S-matrix extraction, as well as capabilities for defining and extracting quantum error parameters. The framework also supports extraction of post-measurement quantum states for use in subsequent circuits or simulators.

A system and method are provided to enable non-quantum experts to schematically represent, simulate and quantify the performance of physically realistic photonic quantum circuits. The framework offers the flexibility for users—not necessarily familiar with the fundamentals of quantum mechanics—to create circuits and work with simple inputs and outputs, while the complexities of manipulating high dimensionality quantum Hilbert spaces supporting photonic and physical quantum object states are handled with the use of purpose-built tools. The tools include a user-friendly method for defining classical photonic circuits which may be coupled to physical objects such as qubits, quantum input states, as well as classical and quantum measurement devices. The tools feature classical-to-quantum S-matrix conversion, quantum S-matrix extraction, as well as capabilities for defining and extracting quantum error parameters. The framework also supports extraction of post-measurement quantum states for use in subsequent circuits or simulators.

Methods, systems and media for simulating or analyzing voltage drops in a power distribution network can use an iterative approach to define a portion of a design around a victim to capture a sufficient collection of aggressors that cause appreciable voltage drop on the victim. This approach can be both computationally efficient and accurate and can limit the size of the data used in simulating dynamic voltage drops in the power distribution network.

A system obtains deterministic results of netlist transformation in a multi-processor parallel computing system. The system receives a netlist. The system determines a set of components representing components with assigned identifiers. The system determines identifiers for remaining components. The system visits a component of the remaining components of the netlist in a topological order starting from the set of components. The system assigns a new identifier to the visited component. The new identifier is generated based on properties of the visited component and a connection of the visited component with at least one component of the set of components. Once the component is assigned an identifier, the system adds the component to the set of components. The system repeats these steps to assign an identifier to remaining components that are not included in the set.

A system obtains deterministic results of netlist transformation in a multi-processor parallel computing system. The system receives a netlist. The system determines a set of components representing components with assigned identifiers. The system determines identifiers for remaining components. The system visits a component of the remaining components of the netlist in a topological order starting from the set of components. The system assigns a new identifier to the visited component. The new identifier is generated based on properties of the visited component and a connection of the visited component with at least one component of the set of components. Once the component is assigned an identifier, the system adds the component to the set of components. The system repeats these steps to assign an identifier to remaining components that are not included in the set.

Methods and systems for verifying a hardware design for a multi-stage component is stall independent. The multi-stage component is configured to receive input data and generate output data by processing the input data at each of a plurality of successive stages wherein each stage is independently enabled by a set of one or more enable signals. The method comprises: for each stage of the plurality of stages from the second stage to the last stage: (a) verifying that a relevant portion of the output data of an instantiation of the hardware design is the same if the instantiation is in the same state when that stage is enabled in a cycle by any set of inputs and any subsequent stages are enabled in subsequent cycles by a first minimal sequence of inputs; and (b) verifying that the relevant portion of the output data of an instantiation of the hardware design is the same if the instantiation is in the same state (i) when that stage is enabled in a cycle and any subsequent stages are enabled in subsequent cycles by a second minimal sequence of inputs and (ii) when that stage is stalled, then that stage is enabled in the next cycle and the subsequent stages are enabled in subsequent cycles by the second minimal sequence of inputs.

Methods and systems for verifying a hardware design for a multi-stage component is stall independent. The multi-stage component is configured to receive input data and generate output data by processing the input data at each of a plurality of successive stages wherein each stage is independently enabled by a set of one or more enable signals. The method comprises: for each stage of the plurality of stages from the second stage to the last stage: (a) verifying that a relevant portion of the output data of an instantiation of the hardware design is the same if the instantiation is in the same state when that stage is enabled in a cycle by any set of inputs and any subsequent stages are enabled in subsequent cycles by a first minimal sequence of inputs; and (b) verifying that the relevant portion of the output data of an instantiation of the hardware design is the same if the instantiation is in the same state (i) when that stage is enabled in a cycle and any subsequent stages are enabled in subsequent cycles by a second minimal sequence of inputs and (ii) when that stage is stalled, then that stage is enabled in the next cycle and the subsequent stages are enabled in subsequent cycles by the second minimal sequence of inputs.

Described is a configuration to remove false paths from an emulation netlist in a chip design under test (DUT). The configuration identifies, in an original netlist, an original subgraph of original logic gates, a subset of inputs (TI), and a subset of outputs (TO). The configuration generates a replicated subgraph of the original subgraph, the replicated subgraph having replicated logic gates corresponding to the original logic gates. The configuration connects the TI with a first replicated logic gate to a constant propagation source and remaining inputs of the replicated logic gates with corresponding original logic gates in the original netlist. The configuration disconnects, in the original netlist, output loads of TO, and connects the output loads of TO with a corresponding equivalent TO in the replicated subgraph. The configuration deletes, in the original netlist, original logic gates unconnected with an output load for TO in the original netlist.

Described is a configuration to remove false paths from an emulation netlist in a chip design under test (DUT). The configuration identifies, in an original netlist, an original subgraph of original logic gates, a subset of inputs (TI), and a subset of outputs (TO). The configuration generates a replicated subgraph of the original subgraph, the replicated subgraph having replicated logic gates corresponding to the original logic gates. The configuration connects the TI with a first replicated logic gate to a constant propagation source and remaining inputs of the replicated logic gates with corresponding original logic gates in the original netlist. The configuration disconnects, in the original netlist, output loads of TO, and connects the output loads of TO with a corresponding equivalent TO in the replicated subgraph. The configuration deletes, in the original netlist, original logic gates unconnected with an output load for TO in the original netlist.