Design of a network-on-chip (NoC) includes searching for a potential deadlock in a topology of the NoC, where the potential deadlock is caused by an external dependency in which input of data into the NoC is dependent on output of data from the NoC. The NoC design further includes modifying the NoC topology to resolve the potential deadlock.

A system and method for implementing and generating a network-on-chip (NoC) topology based on area and timing assessment. A topology of the NoC is defined, approximations of area and timing of the topology without optimization are performed; and an exact, complete register transfer level (RTL) description of the topology is generated if the approximated area and timing satisfy constraints.

A system and method implemented by tool is disclosed. The tool receives input of a network-on-chip (NoC) and the NoC's desired connectivity and efficiently guides the designer through interactive NoC topology editing sessions to ensure the obtained network is both complete and correct during topology creation or modification.

A system can include a nonlinear circuit and a voltage decoder. The nonlinear circuit can perform an operation on an input voltage. The operation can be changed. A voltage decoder can be communicatively coupled to the nonlinear circuit for receiving an output voltage from the nonlinear circuit that results from the operation performed on the input voltage. The voltage decoder can compare the output voltage to a threshold voltage and determine a result of the operation.

A system can include a nonlinear circuit and a voltage decoder. The nonlinear circuit can perform an operation on an input voltage. The operation can be changed. A voltage decoder can be communicatively coupled to the nonlinear circuit for receiving an output voltage from the nonlinear circuit that results from the operation performed on the input voltage. The voltage decoder can compare the output voltage to a threshold voltage and determine a result of the operation.

Systems and methods related to learning-based analyzers (both supervised and unsupervised) for mitigating latch-up in integrated circuits are provided. An example method includes obtaining latch-up data concerning at least one integrated circuit configured to operate under a range of temperature conditions, where the at least one integrated circuit comprises a core portion including at least a plurality of devices each having one or more structural features formed using a lithographic process, and an input/output portion. The method further includes training the learning-based system based on training data derived from the latch-up data and a first layout rule concerning a first spacing between the core portion and the input/output portion. The method further includes using the learning-based system generating a second layout rule concerning the first spacing between the core portion and the input/output portion, where the second layout rule is different from the first layout rule.

According to one aspect of the present disclosure a system and method of enhancing random test case generation during pre-silicon design verification of test models of very large scale integration (VLSI) processors and systems is provided. A test sequence including a specification of at least one target state value for at least one resource of the hardware design model is received and includes a state object having at least one state element defining the target state value for a resource. Instructions are generated to transition the at least one resource from an existing state to the at least one target state value. The instructions are executed according to the test sequence to transition the resources to the defined state. State information on the hardware design model is output to allow a process engineer to determine whether the target state value for the resource was successfully changed.

According to one aspect of the present disclosure a system and method of enhancing random test case generation during pre-silicon design verification of test models of very large scale integration (VLSI) processors and systems is provided. A test sequence including a specification of at least one target state value for at least one resource of the hardware design model is received and includes a state object having at least one state element defining the target state value for a resource. Instructions are generated to transition the at least one resource from an existing state to the at least one target state value. The instructions are executed according to the test sequence to transition the resources to the defined state. State information on the hardware design model is output to allow a process engineer to determine whether the target state value for the resource was successfully changed.

This application discloses a quantum gate optimization method performed by a computer device. The method includes: obtaining an initialized control external field corresponding to a quantum gate; applying the control external field to a quantum bit (qubit) corresponding to the quantum gate, and acquiring actual measurement data of the quantum gate, the actual measurement data being used for reflecting an actual characteristic of the quantum gate; calculating a gradient corresponding to the control external field based on the actual measurement data and ideal data, the ideal data being used for reflecting an ideal characteristic of the quantum gate; and updating the control external field according to the gradient to obtain an updated control external field, the updated control external field being applied to the qubit corresponding to the quantum gate to optimize precision of the quantum gate. The method is a closed-loop optimization solution driven and implemented by data feedback.

Methods and systems for verifying a hardware design for a multi-stage component configured to receive input data and generate output data by processing the input data at each of a plurality of successive stages wherein each stage is independently enabled is stall independent. For each stage from the second stage to the last stage: a relevant portion of the output data of an instantiation of the hardware design is verified as the same if the instantiation is in the same state when that stage is enabled in a cycle by any set of inputs and any subsequent stages are enabled in subsequent cycles by a first minimal sequence of inputs. The relevant portion of the output data of the hardware design is verified as the same if the instantiation is in the same state (i) when that stage is enabled in a cycle and any subsequent stages are enabled in subsequent cycles by a second minimal sequence of inputs and (ii) when that stage is stalled, then that stage is enabled in the next cycle and the subsequent stages are enabled in subsequent cycles by the second minimal sequence of inputs.