Methods and systems for verifying a hardware design for a multi-stage component configured to receive input data and generate output data by processing the input data at each of a plurality of successive stages wherein each stage is independently enabled is stall independent. For each stage from the second stage to the last stage: a relevant portion of the output data of an instantiation of the hardware design is verified as the same if the instantiation is in the same state when that stage is enabled in a cycle by any set of inputs and any subsequent stages are enabled in subsequent cycles by a first minimal sequence of inputs. The relevant portion of the output data of the hardware design is verified as the same if the instantiation is in the same state (i) when that stage is enabled in a cycle and any subsequent stages are enabled in subsequent cycles by a second minimal sequence of inputs and (ii) when that stage is stalled, then that stage is enabled in the next cycle and the subsequent stages are enabled in subsequent cycles by the second minimal sequence of inputs.

The object of the invention is a method of adding another circuit component (1) with operations executable on an FPGA to an FPGA configuration (3), wherein the FPGA configuration (3) already has at least one existing circuit component (2) with operations executable on the FPGA, which is locally distributed in the FPGA configuration (3), with the steps of: Synthesizing the further circuit component (1) to obtain a further netlist, and distributed arranging of the further netlist taking into account the at least one existing circuit component (2) in the FPGA configuration (3).

Methods, apparatus, systems, and articles of manufacture are disclosed for designing hardware. An example apparatus includes processor circuitry to execute machine readable instructions to determine a first hardware architectural configuration of a hardware component based on a design constraint, simulate an execution of the first hardware architectural configuration for a plurality of workloads to generate a respective plurality of objective design spaces, the objective design spaces based on one or more objectives; generate an aggregate score by aggregating a plurality of design space performance indicators, ones of the plurality of design space performance indicators corresponding to respective ones of the plurality of objective design spaces; search a design database based on the aggregate score to identify a second hardware architectural configuration, and predict a performance of the second hardware architectural configuration to generate a performance metric by executing a proxy function corresponding to the second hardware architectural configuration.

Methods for modifying power use of a semiconductor device include receiving, at one or more processors, an activity stream of a simulation of a semiconductor device, the activity stream comprising a stream of signals. Using the one or more processors, integrated circuit actions are recognized from the activity stream, each integrated circuit action representing an abstraction of work done by the semiconductor device. The processor(s) determine one or more values associated with the integrated circuit actions. A model of power use is generated for the semiconductor device, the model based at least in part on the recognized integrated circuit actions and the associated values. Based on an output of the model, power use of the semiconductor device is modified. Other methods and systems related to determining, modeling, and predicting power/energy use of semiconductor devices are also disclosed.

Methods for modifying power use of a semiconductor device include receiving, at one or more processors, an activity stream of a simulation of a semiconductor device, the activity stream comprising a stream of signals. Using the one or more processors, integrated circuit actions are recognized from the activity stream, each integrated circuit action representing an abstraction of work done by the semiconductor device. The processor(s) determine one or more values associated with the integrated circuit actions. A model of power use is generated for the semiconductor device, the model based at least in part on the recognized integrated circuit actions and the associated values. Based on an output of the model, power use of the semiconductor device is modified. Other methods and systems related to determining, modeling, and predicting power/energy use of semiconductor devices are also disclosed.

A technique for designing circuits including receiving a data object representing a circuit for a first process technology, the circuit including a first sub-circuit, the first sub-circuit including a first electrical component and a second electrical component arranged in a first topology; identifying the first sub-circuit in the data object by comparing the first topology to a stored topology, the stored topology associated with the first process technology; identifying a first set of physical parameter values associated with first electrical component and the second electrical component of the first sub-circuit; determining a set of performance parameter values for the first sub-circuit based on a first machine learning model of the first sub-circuit and the identified set of physical parameters; converting the identified first sub-circuit to a second sub-circuit for the second process technology based on the determined set of performance parameter values; and outputting the second sub-circuit.

A technique for designing circuits including receiving a data object representing a circuit for a first process technology, the circuit including a first sub-circuit, the first sub-circuit including a first electrical component and a second electrical component arranged in a first topology; identifying the first sub-circuit in the data object by comparing the first topology to a stored topology, the stored topology associated with the first process technology; identifying a first set of physical parameter values associated with first electrical component and the second electrical component of the first sub-circuit; determining a set of performance parameter values for the first sub-circuit based on a first machine learning model of the first sub-circuit and the identified set of physical parameters; converting the identified first sub-circuit to a second sub-circuit for the second process technology based on the determined set of performance parameter values; and outputting the second sub-circuit.

Embodiments for tuning parameters to a synthesis program are provided. At least one set of parameter settings for the synthesis program is selected. A plurality of identical synthesis jobs for the at least one set of parameter settings is run in an iteration of the synthesis program. Results of the iteration of the synthesis program are analyzed utilizing a tuning optimization cost function. Combinations of the parameter settings are created based on the analysis. At least one synthesis job for is run each of the combinations of the parameter settings in a subsequent iteration of the synthesis program. The analysis of the results, the creating of the combinations of parameter settings, and the running at the at least one synthesis job for each of the combinations of parameter settings are repeated until an exit criteria has been achieved.

Embodiments for tuning parameters to a synthesis program are provided. At least one set of parameter settings for the synthesis program is selected. A plurality of identical synthesis jobs for the at least one set of parameter settings is run in an iteration of the synthesis program. Results of the iteration of the synthesis program are analyzed utilizing a tuning optimization cost function. Combinations of the parameter settings are created based on the analysis. At least one synthesis job for is run each of the combinations of the parameter settings in a subsequent iteration of the synthesis program. The analysis of the results, the creating of the combinations of parameter settings, and the running at the at least one synthesis job for each of the combinations of parameter settings are repeated until an exit criteria has been achieved.

Example embodiments relate to a method for designing integrated circuit based on a computer program including at least one instruction performed by an integrated circuit design system including a processor, the method comprising mapping, by the processor, at least one netlist signal to at least one RTL signal, determining, by the processor, a target netlist signal among the at least one netlist signal, determining, by the processor, a target expression of the target netlist signal using the netlist signal mapped to the at least one RTL signal based on at least a part of the netlist circuit, simulating, by the processor, on the at least one RTL signal, calculating, by the processor, signal simulation predicting information for the target netlist signal using the target expression and generating, by the processor, a design model by designing an integrated circuit using the signal simulation predicting information.