The present invention concerns a method and a tool for designing and validating a data flow system comprising a set of software and/or hardware actors (a.sub.i, a.sub.j) interconnected with each other by unidirectional communication channels (c.sub.i, c.sub.j), the tool comprising: —a modelling interface (11) configured to generate an instance of the system by specifying, in a formal manner, a real-time and reconfigurable data flow, the reconfiguration of the data flow being carried out dynamically by propagating reconfiguration data from one actor to another through the communication channels, —an analysis module (13) configured to prove a predetermined set of behavioral properties of the system by means of a static analysis of the instance, —a refinement interface (15) designed to allocate resources to the instance, thus establishing a configured instance, the allocation of resources being carried out in such a way that an implementation of the system complies with the configured instance, and —a conformity test module (17) configured to verify the conformity of the behaviour of an implementation of the system with respect to the configured instance.

A network device includes processing circuitry configured to: determine whether to initiate a temporal reconfiguration or a spatial reconfiguration of a partial reconfiguration slot on a programmable device, and initiate the temporal reconfiguration or the spatial reconfiguration of the partial reconfiguration slot in response to determining that the temporal reconfiguration or the spatial reconfiguration is to be initiated.

The object of the invention is a method of adding another circuit component (1) with operations executable on an FPGA to an FPGA configuration (3), wherein the FPGA configuration (3) already has at least one existing circuit component (2) with operations executable on the FPGA, which is locally distributed in the FPGA configuration (3), with the steps of: Synthesizing the further circuit component (1) to obtain a further netlist, and distributed arranging of the further netlist taking into account the at least one existing circuit component (2) in the FPGA configuration (3).

The object of the invention is a method of adding another circuit component (1) with operations executable on an FPGA to an FPGA configuration (3), wherein the FPGA configuration (3) already has at least one existing circuit component (2) with operations executable on the FPGA, which is locally distributed in the FPGA configuration (3), with the steps of: Synthesizing the further circuit component (1) to obtain a further netlist, and distributed arranging of the further netlist taking into account the at least one existing circuit component (2) in the FPGA configuration (3).

A circuit system includes a processing integrated circuit die comprising a first die-to-die interface circuit and a memory interface circuit. The circuit system also includes a second integrated circuit die comprising a second die-to-die interface circuit and a compute circuit that performs computations for the processing integrated circuit die. The first and the second die-to-die interface circuits are coupled together. The compute circuit is coupled to exchange information with the memory interface circuit through the first and the second die-to-die interface circuits.

Techniques include retrieving a first structural netlist (SN1) that indicates electronic components, values of programmable parameters, and connections for a first electronic circuit, and retrieving a first placed and routed netlist (PR1) that indicates physical placement of the electronic components and physical routing of connections for SN1. Also retrieved is a second structural netlist (SN2) for a different second electronic circuit. For each component in SN2, a matching component, if any, is found in SN1 based on type of component and inputs that are output from other matching components. A different second placed and routed netlist (PR2) is generated for the second circuit by deriving new placement and routing for only for non-matching components in SN2.

A method and a system for recording an integrated circuit version are provided. The method is adapted to a register in an integrated circuit, which includes the following steps: recording the integrated circuit version with N bits, in which N is an integer greater than 1; and amending only a bit value of at least one bit selected from the N bits that have not been used for denoting any past integrated circuit version each time when the integrated circuit is revised.

A method and a system for recording an integrated circuit version are provided. The method is adapted to a register in an integrated circuit, which includes the following steps: recording the integrated circuit version with N bits, in which N is an integer greater than 1; and amending only a bit value of at least one bit selected from the N bits that have not been used for denoting any past integrated circuit version each time when the integrated circuit is revised.

A method and apparatus for constructing an FPGA chip top-level schematic, and a storage medium are disclosed. The method comprises: integrating several PRIM devices into one grid device; integrating several grid devices into one tile device; abstracting each tile device into a corresponding tile device symbol; according to a predefined interconnection requirement, constructing each tile device symbol into a tile interconnection line symbol of at least one corresponding form; and integrating several tile interconnection line symbols into a top-level schematic. By means of the method, a hierarchical design is used, such that multi-form tile interconnection line symbols can be realized, thereby improving the working efficiency of system integration, and improving the high reliability, verifiability and easy-iteration of system integration.

A method and apparatus for constructing an FPGA chip top-level schematic, and a storage medium are disclosed. The method comprises: integrating several PRIM devices into one grid device; integrating several grid devices into one tile device; abstracting each tile device into a corresponding tile device symbol; according to a predefined interconnection requirement, constructing each tile device symbol into a tile interconnection line symbol of at least one corresponding form; and integrating several tile interconnection line symbols into a top-level schematic. By means of the method, a hierarchical design is used, such that multi-form tile interconnection line symbols can be realized, thereby improving the working efficiency of system integration, and improving the high reliability, verifiability and easy-iteration of system integration.