A battery model construction method includes: a step ST2 for constructing a battery model; steps ST3 and ST4 for evaluating, for each sample battery, the prediction error between a measured value of the SOH and a predicted value according to the battery model, and determining whether there is inherent bias in the prediction error for each sample battery; steps ST5 and ST6 for constructing a first error prediction model associating explanatory variables defined on the basis of usage history parameters with an objective variable, and determining whether a first correlation exists between the measured value of the average prediction error acquired in steps ST3 and ST4 and the predicted value according to the first error prediction model; and a step ST7 for reconstructing the battery model in the case where it is determined that there is bias and that the first correlation exists in steps ST5 and ST6.

This verification processing device is provided with: an inspection unit that performs model inspection on an inspection target model including a plurality of elements; a selection unit that selects at least one of the plurality of elements included in a counterexample outputted as a result of the model inspection; and an exclusion history generation unit that generates exclusion history information indicating an exclusion frequency for each of the plurality of elements. The inspection unit further performs another model inspection on the inspection target model obtained by excluding the selected element. When another counterexample has been outputted as a result of another model inspection, the exclusion history generation unit increases the exclusion frequency of the selected element and updates the exclusion history information. The selection unit selects an element that is high in the exclusion frequency, on the basis of the exclusion history information.

This verification processing device is provided with: an inspection unit that performs model inspection on an inspection target model including a plurality of elements; a selection unit that selects at least one of the plurality of elements included in a counterexample outputted as a result of the model inspection; and an exclusion history generation unit that generates exclusion history information indicating an exclusion frequency for each of the plurality of elements. The inspection unit further performs another model inspection on the inspection target model obtained by excluding the selected element. When another counterexample has been outputted as a result of another model inspection, the exclusion history generation unit increases the exclusion frequency of the selected element and updates the exclusion history information. The selection unit selects an element that is high in the exclusion frequency, on the basis of the exclusion history information.

A system and method for simulating an electronic circuit is disclosed. The method includes creating a finite set of circuit or device parameter points selected from within an n-dimensional parameter space. The method includes determining, for each circuit or device parameter point of the set, a corresponding response value of the performance metric and a corresponding probability of occurrence. The method includes determining, for a predetermined value of the performance metric, the total probability of occurrence.

A system and method for simulating an electronic circuit is disclosed. The method includes creating a finite set of circuit or device parameter points selected from within an n-dimensional parameter space. The method includes determining, for each circuit or device parameter point of the set, a corresponding response value of the performance metric and a corresponding probability of occurrence. The method includes determining, for a predetermined value of the performance metric, the total probability of occurrence.

A computer implemented method of translation of verification commands of an electronic design file of an electronic circuit defined by the electronic design file, comprising receiving, at a processor, the electronic design file defining a functional level electronic design of the electronic circuit, wherein said electronic circuit comprises at least two subsystems and said electronic circuit includes at least two configuration options for the at least two subsystems, receiving along with the electronic design file, at least one analog test harness model having at least one indirect branch contribution statement, translating said at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon said at least one analog test harness model and said electronic design file and generating a netlist for the electronic circuit based at least in part upon said translation of said at least one indirect branch contribution statement.

A computer implemented method of translation of verification commands of an electronic design file of an electronic circuit defined by the electronic design file, comprising receiving, at a processor, the electronic design file defining a functional level electronic design of the electronic circuit, wherein said electronic circuit comprises at least two subsystems and said electronic circuit includes at least two configuration options for the at least two subsystems, receiving along with the electronic design file, at least one analog test harness model having at least one indirect branch contribution statement, translating said at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon said at least one analog test harness model and said electronic design file and generating a netlist for the electronic circuit based at least in part upon said translation of said at least one indirect branch contribution statement.

A system, method, and computer program product for predicting mismatch contribution in an electronic environment. Embodiments may include modeling, using a processor, a discrete output mismatch contribution problem using sparse logistic regression to generate a mismatch contribution model and applying a cross-validation approach to increase a complexity of the mismatch contribution model. Embodiments may further include computing one or more mismatch contribution values from the mismatch contribution model and defining at least one sizing constraint or determining a worst case result associated with a sampling process based upon, at least in part, the one or more mismatch contribution values.

Computer-implemented methods of optimizing a process simulation model that predicts a result of a semiconductor device fabrication operation to process parameter values characterizing the semiconductor device fabrication operation are disclosed. The methods involve generating cost values using a computationally predicted result of the semiconductor device fabrication operation and a metrology result produced, at least in part, by performing the semiconductor device fabrication operation in a reaction chamber operating under a set of fixed process parameter values. The determination of the parameters of the process simulation model may employ pre-process profiles, via optimization of the resultant post-process profiles of the parameters against profile metrology results. Cost values for, e.g., optical scatterometry, scanning electron microscopy and transmission electron microscopy may be used to guide optimization.

Computer-implemented methods of optimizing a process simulation model that predicts a result of a semiconductor device fabrication operation to process parameter values characterizing the semiconductor device fabrication operation are disclosed. The methods involve generating cost values using a computationally predicted result of the semiconductor device fabrication operation and a metrology result produced, at least in part, by performing the semiconductor device fabrication operation in a reaction chamber operating under a set of fixed process parameter values. The determination of the parameters of the process simulation model may employ pre-process profiles, via optimization of the resultant post-process profiles of the parameters against profile metrology results. Cost values for, e.g., optical scatterometry, scanning electron microscopy and transmission electron microscopy may be used to guide optimization.