Patent classifications
G06F30/373
Simulation framework
A method comprises creating an electronic module design having a plurality of electronic components and defining a model of functional behavior of a subset of the plurality of electronic components, the subset of the plurality of electronic components excluding a first electronic component. Functional behavior of the first electronic component is defined in a user-defined functional design intent file based on a first template, and a power behavior of the first electronic component is defined in a user-defined power design intent file based on a second template. A simulation file is generated based on the model of functional behavior and based on the functional behavior and the power behavior of the first electronic component. The simulation file is run to simulate operation of the electronic module design. A performance status is determined of the electronic module design in response to running the simulation file.
Pin sharing for photonic processors
Aspects relate to a photonic processing system, an integrated circuit, and a method of operating an integrated circuit to control components to modulate optical signals. A photonic processing system, comprising: a photonic integrated circuit comprising: a first electrically-controllable photonic component electrically coupling an input pin to a first output pin; and a second electrically-controllable photonic component electrically coupling the input pin to a second output pin.
Pin sharing for photonic processors
Aspects relate to a photonic processing system, an integrated circuit, and a method of operating an integrated circuit to control components to modulate optical signals. A photonic processing system, comprising: a photonic integrated circuit comprising: a first electrically-controllable photonic component electrically coupling an input pin to a first output pin; and a second electrically-controllable photonic component electrically coupling the input pin to a second output pin.
Method, system, and computer program product for implementing electronic design closure with reduction techniques
Disclosed are methods, systems, and articles of manufacture for implementing electronic design closure with reduction techniques. A timing graph and compact timing data for an analysis view of a set of analysis views may be determined for an electronic design. A reduced set of dominant analysis views may be determined based at least in part upon a result of a timing dominance analysis. Timing data may be loaded for at least the reduced set of dominant analysis views; and a design closure task may be performed on the electronic design using at least the timing data and the reduced set of dominance analysis views.
Method, system, and computer program product for implementing electronic design closure with reduction techniques
Disclosed are methods, systems, and articles of manufacture for implementing electronic design closure with reduction techniques. A timing graph and compact timing data for an analysis view of a set of analysis views may be determined for an electronic design. A reduced set of dominant analysis views may be determined based at least in part upon a result of a timing dominance analysis. Timing data may be loaded for at least the reduced set of dominant analysis views; and a design closure task may be performed on the electronic design using at least the timing data and the reduced set of dominance analysis views.
Integrated circuit with a dynamics-based reconfigurable logic block
A system can include a nonlinear circuit and a voltage decoder. The nonlinear circuit can perform an operation on an input voltage. The operation can be changed. A voltage decoder can be communicatively coupled to the nonlinear circuit for receiving an output voltage from the nonlinear circuit that results from the operation performed on the input voltage. The voltage decoder can compare the output voltage to a threshold voltage and determine a result of the operation.
Integrated circuit with a dynamics-based reconfigurable logic block
A system can include a nonlinear circuit and a voltage decoder. The nonlinear circuit can perform an operation on an input voltage. The operation can be changed. A voltage decoder can be communicatively coupled to the nonlinear circuit for receiving an output voltage from the nonlinear circuit that results from the operation performed on the input voltage. The voltage decoder can compare the output voltage to a threshold voltage and determine a result of the operation.
PHOTODETECTOR BEHAVIOR MODELING
Examples disclosed herein relate to photodetector (PD) behavior modeling for process design kit. In some examples, a photodetector behavior model may receive input optical data. Further, the photodetector behavior model may be provided with input values corresponding to input parameters. The photodetector behavior model may identify a set of coefficients from a set of coefficient lookup tables, based on the input values corresponding to input parameters. The photodetector behavior model determines characteristics of one or more model parameters of the photodetector based on the identified set of coefficients. The behavior model determines an output metric indicative of an electrical response of the photodetector, based on the input optical data and the determined characteristics of the one or more model parameters.
DUAL-MODE COMBINED CONTROL METHOD FOR MULTI-INVERTER SYSTEM BASED ON DOUBLE SPLIT TRANSFORMER
A dual-mode combined control method for a multi-inverter system based on a double split transformer is provided. For an extremely-weak grid, the method provides the dual-mode combined control method for a multi-inverter system based on a double split transformer. According to the method, the equivalent grid impedance at a point of common coupling (PCC) of one grid-connected inverter (GCI) in the multi-inverter system based on the double split transformer is obtained with a grid impedance identification algorithm, and the system sequentially operates in a full current source mode, a hybrid mode, and a full voltage source mode according to a gradually increasing equivalent grid impedance, thereby effectively improving the stability of the multi-inverter system based on the double split transformer during variation of the strength of the grid. The method ensures that the system can still operate stably in the extremely-weak grid.
A parallel analog circuit optimization method based on genetic algorithm and machine learning
A parallel analog circuit automatic optimization method based on genetic algorithm and machine learning comprises global optimization based on genetic algorithm and local optimization based on machine learning, with the global optimization and the local optimization performed alternately. The global optimization based on genetic algorithm utilizes parallel SPICE simulations to improve the optimization efficiency while guaranteeing the optimization accuracy, combined with parallel computing. The local optimization based on machine learning establishes a machine learning model near the global optimal point obtained by the global optimization, and uses the machine learning model to replace the SPICE simulator, thus reducing the time costs brought by a large number of simulations.