A computing system implementing a design verification system can detect multiple analog design blocks in a circuit design describing an electronic device. The design verification system can generate equivalent networks for the analog design blocks using different sets of the parameters of the analog design blocks by selectively collapsing nodes and braches in the analog design blocks based on values of the different sets of the parameters. The equivalent networks can correspond to behavioral topologies of the analog design blocks having the different sets of the parameters. The design verification system can selectively compile a subset of the analog design blocks into multiple compiled variant models based on a comparison of the equivalent networks. The design verification system can include an analog simulator to simulate the analog design blocks in the circuit design using the compiled variant models.

This invention relates to a robust optimal design method for photovoltaic cells. Firstly, the deterministic optimal model is established, which is solved by Monte Carlo method to obtain the maximum output power value of optimization objective and its corresponding design variable value, and then the design variable value obtained from deterministic optimization is deemed as the initial point of the mean value of the robust optimal design variable. Later, the robust optimal model is solved by Monte Carlo method in order to obtain the mean value of design variable, and then appropriate materials and manufacturing techniques are selected for corresponding photovoltaic components according to the design variable obtained, so as to achieve the robust optimal design of photovoltaic cells. In fact, this invention improves the output stability and reliability of photovoltaic cells.

This invention relates to a robust optimal design method for photovoltaic cells. Firstly, the deterministic optimal model is established, which is solved by Monte Carlo method to obtain the maximum output power value of optimization objective and its corresponding design variable value, and then the design variable value obtained from deterministic optimization is deemed as the initial point of the mean value of the robust optimal design variable. Later, the robust optimal model is solved by Monte Carlo method in order to obtain the mean value of design variable, and then appropriate materials and manufacturing techniques are selected for corresponding photovoltaic components according to the design variable obtained, so as to achieve the robust optimal design of photovoltaic cells. In fact, this invention improves the output stability and reliability of photovoltaic cells.

Aspects relate to a photonic processing system, an integrated circuit, and a method of operating an integrated circuit to control components to modulate optical signals. A photonic processing system, comprising: a photonic integrated circuit comprising: a first electrically-controllable photonic component electrically coupling an input pin to a first output pin; and a second electrically-controllable photonic component electrically coupling the input pin to a second output pin.

Aspects relate to a photonic processing system, an integrated circuit, and a method of operating an integrated circuit to control components to modulate optical signals. A photonic processing system, comprising: a photonic integrated circuit comprising: a first electrically-controllable photonic component electrically coupling an input pin to a first output pin; and a second electrically-controllable photonic component electrically coupling the input pin to a second output pin.

An impedance matching method includes following operations: providing load impedance data of a network interface controller chip; providing characteristic data of a network transformer, in which the network transformer is configured to be connected to the network interface controller chip via a transmission line on a printed circuit board, and a first predetermined data rate of the network transformer is lower than a second predetermined data rate of the network interface controller chip; adjusting an arrangement among the load impedance data, a length of the transmission line, and a width of the transmission line according to the characteristic data to adjust an impedance matching between the network transformer and the network interface controller chip, in order to make the network transformer meet a predetermined requirement corresponding to the second predetermined data rate; and storing the arrangement to be design data for fabricating the printed circuit board.

An apparatus includes circuitry configured to calculate first parameters for determining a structure of a first antenna device based on a specification value set for the first antenna device to be a target of performance evaluation, acquire a communication frequency based on first parameters, calculate an allowable range of deviation of the communication frequency satisfying a specified performance evaluation standard of the first antenna device, determine a structure of a second antenna device as a reference model, and obtain a change amount corresponding to change in the communication frequency in the allowable range of two second parameters having a correlation with each other, and acquire a relational expression of two first parameters of first parameters that correspond to the two second parameters and that have a correlation with each other, and two first parameters based on the change amount and that have the correlation with each other.

A filter debugging method, a device, an electronic apparatus and a readable storage medium are provided. The filter debugging method includes: step S1: inputting a current hole parameter and a current index value of a filter into a policy network which is pre-trained; step S2: determining, by the policy network, a target hole to be polished of the filter, according to the current hole parameter and the current index value of the filter; step S3: controlling a mechanical arm to polish the target hole of the filter; and step S4: determining whether the filter is qualified according to an index value of the polished filter; in a case that the filter is qualified, ending a process including the steps S1 to S4; in a case that the filter is unqualified, performing the steps S1 to S4 circularly until the filter is qualified.

A system and method for the automatic placement of superconducting devices determines an arrangement of a series of Josephson junctions between a start point and an end point of an inductive wiring run on a superconducting circuit layout having a plurality of discrete Josephson junction placement sites by determining costs of placing each Josephson junction of the series of Josephson junctions at the plurality of discrete Josephson junction placement sites between the start point and the end point of the inductive wiring run based at least on a comparison of a target inductance value to inductances of wires connecting to the Josephson junction and selecting sites from the plurality of discrete Josephson junction placement sites to place each Josephson junction corresponding to the arrangement of the series of Josephson junctions with the least determined cost for the inductive wiring run.

A system and method for the automatic placement of superconducting devices determines an arrangement of a series of Josephson junctions between a start point and an end point of an inductive wiring run on a superconducting circuit layout having a plurality of discrete Josephson junction placement sites by determining costs of placing each Josephson junction of the series of Josephson junctions at the plurality of discrete Josephson junction placement sites between the start point and the end point of the inductive wiring run based at least on a comparison of a target inductance value to inductances of wires connecting to the Josephson junction and selecting sites from the plurality of discrete Josephson junction placement sites to place each Josephson junction corresponding to the arrangement of the series of Josephson junctions with the least determined cost for the inductive wiring run.