An integrated circuit (IC) device includes a substrate, and a cell over the substrate. The cell includes at least one active region and at least one gate region extending across the at least one active region. The cell further includes at least one input/output (IO) pattern configured to electrically couple one or more of the at least one active region and the at least one gate region to external circuitry outside the cell. The at least one IO pattern extends obliquely to both the at least one active region and the at least one gate region.

An assembling method for a multi-core cable having a plurality of electrical insulated wires is designed to connect one-end-portions of the electrical insulated wires to electrode patterns, respectively, of one circuit board, correspondingly connect other-end-portions of the electrical insulated wires to electrode patterns, respectively, of the other circuit board, compute intersection coefficients on one end side and the other of the cable, and iterate interchanging connecting destinations for the one-end-portions of the electrical insulated wires, correspondingly interchanging connecting destinations for the other-end-portions of the electrical insulated wires, and computing the intersection coefficients on the one end side and the other of the cable. The connecting destinations for the electrical insulated wires to the electrode patterns are determined in such a manner that a maximum intersection coefficient denoting either larger one of the respective intersection coefficients of the one end side and the other of the cable is made small.

A board design assistance device includes a design data acquirer to acquire design data for a printed circuit board, a first determiner to determine, based on the design data for the printed circuit board, whether a lengthwise direction of board fiber in the printed circuit board is perpendicular to a longitudinal direction of an electronic component mounted on the printed circuit board, a second determiner to determine, based on the design data for the printed circuit board, whether a wire is routed crosswise from a pad receiving the electronic component mounted on the printed circuit board, and a notifier to provide a notification including error information specifying an electronic component determined to have a longitudinal direction not perpendicular to the lengthwise direction of the board fiber and determined to be connected to a pad from which a wire is not routed crosswise.

A board design assistance device includes a design data acquirer to acquire design data for a printed circuit board, a first determiner to determine, based on the design data for the printed circuit board, whether a lengthwise direction of board fiber in the printed circuit board is perpendicular to a longitudinal direction of an electronic component mounted on the printed circuit board, a second determiner to determine, based on the design data for the printed circuit board, whether a wire is routed crosswise from a pad receiving the electronic component mounted on the printed circuit board, and a notifier to provide a notification including error information specifying an electronic component determined to have a longitudinal direction not perpendicular to the lengthwise direction of the board fiber and determined to be connected to a pad from which a wire is not routed crosswise.

A sub route flow is a route flow different from a main route flow in testing of a semiconductor product. A method for configuring a sub route flow includes: determining at least one test item of the semiconductor product; obtaining a first test template corresponding to the test item, wherein the first test template includes preset test parameters; displaying the preset test parameters; receiving test parameters adjusted according to the preset test parameters; configuring current test parameters of the test item according to the adjusted test parameters; and forming the sub route flow of the semiconductor product according to the current test parameters of the test item.

A sub route flow is a route flow different from a main route flow in testing of a semiconductor product. A method for configuring a sub route flow includes: determining at least one test item of the semiconductor product; obtaining a first test template corresponding to the test item, wherein the first test template includes preset test parameters; displaying the preset test parameters; receiving test parameters adjusted according to the preset test parameters; configuring current test parameters of the test item according to the adjusted test parameters; and forming the sub route flow of the semiconductor product according to the current test parameters of the test item.

In accordance with various embodiments and aspects of the invention, systems and methods are disclosed that create a system-level address map and create a report. A system description of an electronic system (e.g., integrated circuit (IC)) is received that includes configuration parameters. A tree representation of the system is created based on the interconnect of the system. Each port of the system is assigned a tree node. To create a corresponding system-level address map, the tree representation is traversed from target(s) to initiator(s), calculating the address transformation at each node. A report of the system-level address map is created, and defects such as address duplication, missing addresses, etc. can be identified and reported to the user.

In accordance with various embodiments and aspects of the invention, systems and methods are disclosed that create a system-level address map and create a report. A system description of an electronic system (e.g., integrated circuit (IC)) is received that includes configuration parameters. A tree representation of the system is created based on the interconnect of the system. Each port of the system is assigned a tree node. To create a corresponding system-level address map, the tree representation is traversed from target(s) to initiator(s), calculating the address transformation at each node. A report of the system-level address map is created, and defects such as address duplication, missing addresses, etc. can be identified and reported to the user.

The following description is directed to a logic repository service. In one example, a method of a logic repository service can include receiving a first request to generate configuration data for configurable hardware using a specification for application logic of the configurable hardware. The method can include generating the configuration data for the configurable hardware. The configuration data can include data for implementing the application logic. The method can include receiving a second request to download the configuration data to a host server computer comprising the configurable hardware. The method can include transmitting the configuration data to the host server computer in response to the second request so that the configurable hardware is configured with the host logic and the application logic.

The following description is directed to a logic repository service. In one example, a method of a logic repository service can include receiving a first request to generate configuration data for configurable hardware using a specification for application logic of the configurable hardware. The method can include generating the configuration data for the configurable hardware. The configuration data can include data for implementing the application logic. The method can include receiving a second request to download the configuration data to a host server computer comprising the configurable hardware. The method can include transmitting the configuration data to the host server computer in response to the second request so that the configurable hardware is configured with the host logic and the application logic.