A wiring quality test method includes the following: a respective wiring result topological structure and a respective expected topological structure corresponding to each signal to be tested in a set of signals to be tested are determined based on a wiring layout; for each signal to be tested, the wiring result topological structure is compared with the expected topological structure, to obtain a topological structure comparison result corresponding to the signal to be tested; in response to determining that the topological structure comparison result is greater than a preset threshold, it is determined a test result indicating that wiring for the signal to be tested is inappropriate; and a quality test report is generated based on test results of the signals to be tested.

A method includes accessing a display structure for manufacturing a display panel for an under-display camera (UDC) system. The method further includes computing a point spread function (PSF) of the UDC system with the display structure and computing a metric to evaluate performance of the display structure based on the PSF. The method further includes determining that the metric does not satisfy selection criteria for using the display structure for manufacturing the display panel for the UDC system and in response to the determination, iteratively optimizing the display structure, using an automated searching process, until the metric satisfies the selection criteria. The method further includes generating an optimized display structure responsive to completion of the automated searching process. The optimized display structure is used for manufacturing the display panel for the UDC system.

A method includes accessing a display structure for manufacturing a display panel for an under-display camera (UDC) system. The method further includes computing a point spread function (PSF) of the UDC system with the display structure and computing a metric to evaluate performance of the display structure based on the PSF. The method further includes determining that the metric does not satisfy selection criteria for using the display structure for manufacturing the display panel for the UDC system and in response to the determination, iteratively optimizing the display structure, using an automated searching process, until the metric satisfies the selection criteria. The method further includes generating an optimized display structure responsive to completion of the automated searching process. The optimized display structure is used for manufacturing the display panel for the UDC system.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip placement. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip placement, comprising placing a respective macro node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the macro node to be placed at the time step to a position from the plurality of positions using the score distribution.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip placement. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip placement, comprising placing a respective macro node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the macro node to be placed at the time step to a position from the plurality of positions using the score distribution.

An apparatus to facilitate scalable runtime validation for on-device design rule checks is disclosed. The apparatus includes a memory to store a contention set, one or more multiplexors, and a validator communicably coupled to the memory. In one implementation, the validator is to: receive design rule information for the one or more multiplexers, the design rule information referencing the contention set; analyze, using the design rule information, a user bitstream against the contention set at a programming time of the apparatus, the user bitstream for programming the one or more multiplexors; and provide an error indication responsive to identifying a match between the user bitstream and the contention set.

An apparatus to facilitate scalable runtime validation for on-device design rule checks is disclosed. The apparatus includes a memory to store a contention set, one or more multiplexors, and a validator communicably coupled to the memory. In one implementation, the validator is to: receive design rule information for the one or more multiplexers, the design rule information referencing the contention set; analyze, using the design rule information, a user bitstream against the contention set at a programming time of the apparatus, the user bitstream for programming the one or more multiplexors; and provide an error indication responsive to identifying a match between the user bitstream and the contention set.

Techniques for designing and implementing networks-on-chip (NoCs) are provided. For example, a computer-implemented method for programming a network-on-chip (NoC) onto an integrated circuit includes determining a first portion of a plurality of registers to potentially be included in a NoC design, determining routing information regarding datapaths between registers of the first portion of the plurality of registers, and determining an expected performance associated with the first portion of the plurality of registers. The method also includes determining whether the expected performance is within a threshold range, including the first portion of the plurality of registers and the datapaths in the NoC design after determining that the expected performance is within the threshold range, and generating instructions configured to cause circuitry corresponding to the NoC design to be implemented on the integrated circuit.

Techniques for designing and implementing networks-on-chip (NoCs) are provided. For example, a computer-implemented method for programming a network-on-chip (NoC) onto an integrated circuit includes determining a first portion of a plurality of registers to potentially be included in a NoC design, determining routing information regarding datapaths between registers of the first portion of the plurality of registers, and determining an expected performance associated with the first portion of the plurality of registers. The method also includes determining whether the expected performance is within a threshold range, including the first portion of the plurality of registers and the datapaths in the NoC design after determining that the expected performance is within the threshold range, and generating instructions configured to cause circuitry corresponding to the NoC design to be implemented on the integrated circuit.

A method and an apparatus of designing an integrated circuit are provided. The method includes: S1, loading a power fill to a circuit layout with original metal lines; S2, checking whether a current layout includes a region with a spacing error; if yes, performing S3; otherwise, outputting the current layout; and S3, pruning a power fill shape corresponding to the region with a spacing error by a predetermined spacing width delta, and returning to the S2.