Fully homomorphic encryption integrated circuit (IC) chips, systems and associated methods are disclosed. In one embodiment, a method of operation for a number theoretic transform (NTT) butterfly circuit is disclosed. The (NTT) butterfly circuit includes a high input word path cross-coupled with a low word path. The high input word path includes a first adder/subtractor, and a first multiplier. The low input word path includes a second adder/subtractor, and a second multiplier. The method includes selectively bypassing the second adder/subtractor and the second multiplier, and reconfiguring the low and high input word paths into different logic processing units in response to different mode control signals.

A neural network apparatus includes: a first processing circuit and a second processing circuit each configured to perform a vector-by-matrix multiplication (VMM) operation on a weight and an input activation; a first register configured to store an output of the first processing circuit; an adder configured to add an output of the first register and an output of the second processing circuit; a second register configured to store an output of the adder; and an input circuit configured to input a same input activation to the first processing circuit and the second processing circuit and control the first processing circuit and the second processing circuit.

Crossbar arrays perform analog vector-matrix multiplication naturally and provide a building block for modern computing systems. In many applications, the weights stored in the crossbar array are learned off-line and then stored on embedded devices. After the weights are learned, they do not change. Since the weights do not change in these applications, this disclosure envisions a new implementation for the processing elements of the crossbar array.

A multiplier device for binary magnetic applied fields uses Interlayer Exchange Coupling (IEC) structure where two layers of ferromagnetic material are separated from each other by non-magnetic layers of electrically conductive material of atomic thickness, sufficient to generate anti-magnetic response in a magnetized layer. A plurality of regions on a top surface are activated with a magnetic field in a first direction for a 1 value and in an opposite direction for a 0 value, the multiplication result presented as magnetic field direction on a plurality of output ferromagnetic regions.

A neural network circuit includes a memory device in which memristors being variable resistance elements are connected in a matrix and serve as memory elements of the memory device. The neural network circuit further includes a voltage application device arranged to apply a bias voltage to the memory device and current-voltage (I-V) conversion amplification circuits arranged to convert currents flowing via the memory elements into voltages and output the voltage. A feedback resistor of a respective I-V conversion amplification circuit includes a memristor. The feedback resistor of a respective I-V conversion amplification circuit and the memory elements acting as an input resistor of the I-V conversion amplification circuit are connected to align a polarity direction of the memristor of the feedback resistor and polarity directions of the memristors of the memory elements acting as the input resistor.

A processing-in-memory (PIM) device includes a plurality of storage regions, a global buffer, and a plurality of multiplication/accumulation (MAC) circuits. The plurality of MAC circuits are configured to perform a MAC operation of first data from the plurality of storage regions and second data from the global buffer. Each of the plurality of MAC circuits is categorized as either an active MAC circuit or an inactive MAC circuit. The MAC operation includes a selective MAC operation which is selectively performed by the active MAC circuit.

A 2D array-based neuromorphic processor includes: axon circuits each being configured to receive a first input corresponding to one bit from among bits indicating n-bit activation; first direction lines extending in a first direction from the axon circuits; second direction lines intersecting the first direction lines; synapse circuits disposed at intersections of the first direction lines and the second direction lines, and each being configured to store a second input corresponding to one bit from among bits indicating an m-bit weight and to output operation values of the first input and the second input; and neuron circuits connected to the second direction lines, each of the neuron circuits being configured to receive an operation value output from at least one of the synapse circuits, based on time information assigned individually to the synapse circuits, and to perform a multi-bit operation by using the operation values and the time information.

Data processing apparatus having a binary neural network, BNN, circuitry to implement a BNN; the BNN circuitry having at least one instance of hidden layer circuitry responsive to trained one-bit weight values and input data values to generate a hidden layer output signal; each input data value has a one-hot n-bit data value, where n is an integer greater than one; the hidden layer circuitry is configured to generate the hidden layer output signal dependent upon an intermediate result of a selective inversion operation applied to each bit of a given input data value; the hidden layer circuitry has circuitry to generate a respective intermediate result as a first predetermined result value for the given input data value; and, for a group of trained one-bit weight values, circuitry to generate a respective intermediate result as a second predetermined result value for the given input data value.

A universal quantum computer may be emulated by a classical computing system that uses an electronic signal of bounded duration and amplitude to represent an arbitrary initial quantum state. The initial quantum state may be specified by inputs provided to the system and may be encoded in the signal, which is derived from a collection of phase-coherent coherent basis signals. Unitary quantum computing gate operations, including logical operations on qubits or operations that change the phase of a qubit, may be performed using analog electronic circuits within the quantum computing emulation device. These circuits, which may apply a matrix transformation to the signals representing the initial quantum state, may include four-quadrant multipliers, operational amplifiers, and analog filters. A measurement component within the quantum computing emulation device may produce a digital signal output representing the transformed quantum state. The gate operation(s) performed may be selected from among multiple supported operations.

A multiply and accumulate calculation device includes a multiple calculation unit and a accumulate calculation unit. The multiple calculation unit includes a plurality of multiple calculation elements, which are variable resistance elements, and at least one reference element. The accumulate calculation unit includes an output detector configured to detect a total value of at least outputs from the plurality of multiple calculation elements. Each of the plurality of multiple calculation elements is a magnetoresistance effect element including a magnetized free layer having a magnetic domain wall, a magnetization fixed layer in which a magnetization direction is fixed, and a nonmagnetic layer sandwiched between the magnetized free layer and the magnetized fixed layer. The reference element is a reference magnetoresistance effect element having a magnetization free layer that does not have the magnetic domain wall.