A circuit for multiplying a number N of first operands each by a corresponding second operand, and for adding the products of the multiplications, with N2; the circuit comprising: N input conductors; N programmable conductance circuits connected each between one of the input conductors and at least one output conductor; each programmable conductance circuit being arranged to be programmable at a value depending in a known manner from one of the first operands; each input conductor being arranged to receive from an input circuit an input train of voltage spikes having a spike rate that derives in a known manner from one of the second operands; and at least one output circuit arranged to generate an output train of voltage spikes having a spike rate that derives in a known manner from a sum over time of the spikes received on the at least one output conductor.

Fully homomorphic encryption integrated circuit (IC) chips, systems and associated methods are disclosed. In one embodiment, a method of operation for a number theoretic transform (NTT) butterfly circuit is disclosed. The (NTT) butterfly circuit includes a high input word path cross-coupled with a low word path. The high input word path includes a first adder/subtractor, and a first multiplier. The low input word path includes a second adder/subtractor, and a second multiplier. The method includes selectively bypassing the second adder/subtractor and the second multiplier, and reconfiguring the low and high input word paths into different logic processing units in response to different mode control signals.

A multiply and accumulate calculation device includes a multiple calculation unit and a accumulate calculation unit. The multiple calculation unit includes a plurality of multiple calculation elements, which are variable resistance elements, and at least one reference element. The accumulate calculation unit includes an output detector configured to detect a total value of at least outputs from the plurality of multiple calculation elements. Each of the plurality of multiple calculation elements is a magnetoresistance effect element including a magnetized free layer having a magnetic domain wall, a magnetization fixed layer in which a magnetization direction is fixed, and a nonmagnetic layer sandwiched between the magnetized free layer and the magnetized fixed layer. The reference element is a reference magnetoresistance effect element having a magnetization free layer that does not have the magnetic domain wall.

A multiply-accumulate operation apparatus is capable of sufficiently restraining a sneak current when employing a precharge method where the magnitude of an electric current flowing through an output line is detected. In a synapse operation section, memory cells storing respective synaptic connection weights are arranged in rows and columns. Output lines are connected to memory cells in the corresponding column, and input lines are connected to memory cells in the corresponding row. Each output line is precharged, and then its electric potential is decreased during the corresponding memory cells flow cell currents corresponding to their synaptic connection weights. A memory element of each memory cell includes a memory transistor, a drain side transistor, and a source side transistor connected in series, and is connected between the corresponding input and output line. The memory transistor stores a synaptic connection weight according to the amount of charge in a charge storage layer.

A memory device includes an array of composite memory units. At least one of the composite memory units comprises a first memory cell of a first type, a second memory cell of a second type, a first intra-unit data path connecting the first memory cell to the second memory cell, and a first data path control switch. The first data path control switch is responsive to a data transfer enable signal which enables data transfer between the first memory cell and the second memory cell through the first intra-unit data path.

Examples of the present disclosure provide apparatuses and methods for performing multiplication operations in a memory. An example method comprises performing a multiplication operation on a first element stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second element stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array. The method can include a number operations performed without transferring data via an input/output (I/O) line.

Fully homomorphic encryption integrated circuit (IC) chips, systems and associated methods are disclosed. In one embodiment, a method of operation for a number theoretic transform (NTT) butterfly circuit is disclosed. The (NTT) butterfly circuit includes a high input word path cross-coupled with a low word path. The high input word path includes a first adder/subtractor, and a first multiplier. The low input word path includes a second adder/subtractor, and a second multiplier. The method includes selectively bypassing the second adder/subtractor and the second multiplier, and reconfiguring the low and high input word paths into different logic processing units in response to different mode control signals.

Many signal processing, machine learning and scientific computing applications require a large number of multiply-accumulate (MAC) operations. This type of operation is demanding in both computation and memory. Process in memory has been proposed as a new technique that computes directly on a large array of data in place, to eliminate expensive data movement overhead. To enable parallel multi-bit MAC operations, both width- and level-modulating memory word lines are applied. To improve performance and provide tolerance against process-voltage-temperature variations, a delay-locked loop is used to generate fine unit pulses for driving memory word lines and a dual-ramp Single-slope ADC is used to convert bit line outputs. The concept is prototyped in a 180 nm CMOS test chip made of four 32064 compute-SRAMs, each supporting 128 parallel 5 b5 b MACs with 32 5 b output ADCs and consuming 16.6 mW at 200 MHz.

Real time cognitive monitoring of correlations between variables including receiving, by a circuit, a first set of data results and a second set of data results, wherein each set of data results comprises binary data points; adding a unit of charge to a collection capacitor on the circuit for each of the first set of data results that indicates a positive data point; removing a unit of charge from the collection capacitor for each of the second set of data results that indicates a positive data point; and triggering a first sense amp on the circuit if the charge on the collection capacitor exceeds a high charge threshold, indicating that the positive data points in the first set of data results is greater than the positive data points in the second set of data results to a first statistical significance.

A multiplier circuit can be fabricated within an integrated circuit and can draw a product output node to a voltage proportional to a product of first and second binary numbers received at two sets of inputs. The multiplier circuit includes a first set of scaled capacitors connected to an output of a multiplexor and to a local product output node. Each multiplexor is connected to a second set of scaled capacitors configured to generate an analog voltage in proportion to the value of the first binary number. Each scaled capacitor of first set of scaled capacitors has a capacitance proportional to a significance of a respective bit of the second binary number. The multiplier circuit includes a reference capacitor connected to ground and the product output node, and a reset circuit configured to draw, in response to a RESET signal, the product output node to ground.