Disclosed is a cache control device which makes it possible to, even when a failure is occurred in a cache, reduce a risk that information is lost due to the failure. A cache control device 1 includes a monitor unit 2 that monitors an occurrence of a failure of a plurality of storage devices which constitute a cache; and a control unit 3 that determines superiority or inferiority of the storage devices on the basis of life-span information and failure information which are related to the storage devices, and that changes a configuration of the cache in accordance with a result of the determination.

A system and method for maintaining operation of a storage array with one or more failed storage devices and for quickly recovering when failing devices are replaced are provided. In some embodiments, the method includes receiving a data transaction directed to a volume and determining that a storage device associated with the volume is inoperable. In response to determining that the storage device is inoperable, a data extent is recorded in a change log in a storage controller cache. The data extent is associated with the data transaction and allocated to the storage device that is inoperable. The data transaction is performed using at least one other storage device associated with the volume, and data allocated to the storage device is subsequently reconstructed using the recorded data extent.

Systems and methods are disclosed that allow for transparently recovering from an uncorrected multi-bit error of arbitrary length located at a memory address. Storing one or more parity pages, for a set of pages in system memory, such that a page in the set of pages may be reconstructed using one of the parity pages is disclosed. Storing an indication of one or more page'disk location such that the one or more pages may be reconstructed by refilling the page from disk is also disclosed.

Solutions for providing increased performance of write operations that are candidates for coalesced writes but don't end up writing an entire row of new data. In accordance with some embodiments, a controller can perform a pre-read operation early, in some cases as soon as the write request received from the host is identified as a candidate for write coalescing.

A system for performing modular parity caching includes a computing platform having a hardware processor and a system memory storing software code. The hardware processor executes the software code to receive a dataset, identify a first storage medium for storing the dataset, determine a target data size for a data subset, and partition the dataset into a plurality of data subsets each having the target data size. The hardware processor further executes the software code to compute, using the data subsets, a parity bit for each data field occupying the same position in each of the data subsets to provide a plurality of parity bits each corresponding respectively to one data field occupying the same position in each of the data subsets, store each of the data subsets in the first storage medium, and store the parity bits as a parity cache in a second storage medium.

A system for performing modular parity caching includes a computing platform having a hardware processor and a system memory storing software code. The hardware processor executes the software code to receive a dataset, identify a first storage medium for storing the dataset, determine a target data size for a data subset, and partition the dataset into a plurality of data subsets each having the target data size. The hardware processor further executes the software code to compute, using the data subsets, a parity bit for each data field occupying the same position in each of the data subsets to provide a plurality of parity bits each corresponding respectively to one data field occupying the same position in each of the data subsets, store each of the data subsets in the first storage medium, and store the parity bits as a parity cache in a second storage medium.

There are provided methods and systems for improving RAS features of a memory device. For example, there is provided a system that includes a memory and a memory side cache. The system further includes a processor that is configured to minimize accesses to the memory by executing certain operations. The operations can include computing a new parity based on old data, new data, and an old parity in response to data from the memory side cache being written to the memory.