An information processing apparatus includes a network interface, a storage device, and a processor. The processor is configured to assign a plurality of zones in the storage device. Each of the zones is a contiguous physical address range of the storage device that is mapped to a contiguous logical address range. The processor is configured to generate zone management information for each of the plurality of zones, store content received from the origin server via the network interface, in one of writable zones and update a writable address of the zone management information for the one of the writable zones. The processor is configured to operate to transmit the received content, and control the storage device to delete data stored therein in units of a zone upon a predetermined cache clearing criteria being met.

An apparatus is described. The apparatus includes a memory controller to interface with a multi-level memory, where, an upper level of the multi-level memory is to act as a cache for a lower level of the multi-level memory. The memory controller has circuitry to determine: i) an original address of a slot in the upper level of memory from an address of a memory request in a direct mapped fashion; ii) a miss in the cache for the request because the slot is pinned with data from another address that competes with the address; iii) a partner slot of the slot in the cache in response to the miss; iv) whether there is a hit or miss in the partner slot in the cache for the request.

Modifications to caching performed between different services may be determined. A history of requests and responses between the different services may be obtained. The history may be evaluated to determine respective frequencies of parameters between the services. The frequencies of parameters may be evaluated to determine one or more modifications to caching among the different services. The modifications may be provided in order to be applied to change caching performance for subsequent requests.

Methods and apparatus implementing Hardware/Software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloads. The apparatus include multi-core processors with multi-level cache hierarchies including and L1 and L2 cache for each core and a shared last-level cache (LLC). One or more machine-level instructions are provided for proactively demoting cachelines from lower cache levels to higher cache levels, including demoting cachelines from L1/L2 caches to an LLC. Techniques are also provided for implementing hardware/software co-optimization in multi-socket NUMA architecture system, wherein cachelines may be selectively demoted and pushed to an LLC in a remote socket. In addition, techniques are disclosure for implementing early snooping in multi-socket systems to reduce latency when accessing cachelines on remote sockets.

Aspects of managing Translation Lookaside Buffer (TLB) units are described herein. The aspects may include a memory management unit (MMU) that includes one or more TLB units and a control unit. The control unit may be configured to identify one from the one or more TLB units based on a stream identification (ID) included in a received virtual address and, further, to identify a frame number in the identified TLB unit. A physical address may be generated by the control unit based on the frame number and an offset included in the virtual address.

The invention discloses a prefetch-adaptive intelligent cache replacement policy for high performance, in the presence of hardware prefetching, a prefetch request and a demand request are distinguished, a prefetch predictor based on an ISVM (Integer Support Vector Machine) is used for carrying out re-reference interval prediction on a cache line of prefetching access loading, and a demand predictor based on an ISVM is utilized to carry out re-reference interval prediction on a cache line of demand access loading. A PC of a current access load instruction and PCs of past load instructions in an access historical record are input, different ISVM predictors are designed for prefetch and demand requests, reuse prediction is performed on a loaded cache line by taking a request type as granularity, the accuracy of cache line reuse prediction in the presence of prefetching is improved, and performance benefits from hardware prefetching and cache replacement is better fused.

A method, a computing device, and a non-transitory machine-readable medium for modifying cache settings in the array cache are provided. Cache settings are set in an array cache, such that the array cache caches data in an input/output (I/O) stream based on the cache settings. Multiple cache simulators simulate the caching the data from the I/O stream in the array cache using different cache settings in parallel with the array cache. The cache settings in the array cache are replaced with the cache settings from one of the cache simulators based on the determination that the cache simulators increase effectiveness of caching data in the array cache.

Techniques for storing data involve estimating a hit ratio of a digest cache associated with a target storage device, the digest cache recording a digest of data that is stored in the target storage device after preprocessing; generating, according to a determination that the hit ratio is lower than a predetermined threshold, a digest for target data to be stored and performing the preprocessing; and storing, according to a determination that the digest of the target data is missing in the digest cache, the preprocessed target data in the target storage device, and recording the digest of the target data in the digest cache. Such techniques can achieve good system performance in both cases of high data repetition and low data repetition.

A technology for estimating one or more cache hit rates. An implementation includes receiving a request-response pair, calculating a fingerprint for the request-response pair, storing the fingerprint, and determining whether the fingerprint is a member of a bloom filter.

A core simulator includes one or more simulated processors, a trace-based traffic generator, and a simulated memory subsystem. Each simulated processor includes a core element and at least one lower-level cache excluded from the core element. The trace-based traffic generator includes a plurality of modeled caches that model the at least lower-level cache without modeling the core element. The trace-based traffic generator is configured to receive at least one workload trace and based on the workload trace simulate actual memory traffic to be processed by the simulated memory subsystem. The simulated memory subsystem is shared between the at least one simulated processor and the trace-based traffic generator. The trace-based traffic generator performs a data exchange with the memory subsystem based on the at least one workload trace. The data exchange impacts a measured performance of the at least one simulated processor.