A varied least recently used (VLRU) caching technique is used to enable print data to be available at a cache of a client for printing, even after an agent performs a deletion of a hash value for the print data at a cache of the agent. The deletion of the print data (cached at the cache of the client) is postponed at the client device via the use of a waiting list, so that the cached print data can be printed at a physical printer of the client, in response to receiving a delayed print job from the agent that specifies the hash value as a result of a deduplication process performed by the agent.

Example implementations relate to metadata operations in a storage system. An example storage system includes a machine-readable storage storing instructions executable by a processor to determine to generate a synthetic full backup based on data stream representations of a plurality of data streams. The instructions are also executable to, in response to a determination to generate the synthetic full backup, create a logical group including the data stream representations. The instructions are also executable to specify a cache resource allocation for the logical group, and generate the synthetic full backup from data stream representations using an amount of a cache resource limited by the cache resource allocation for the logical group.

Methods, apparatus, systems and articles of manufacture are disclosed for allocation in a victim cache system. An example apparatus includes a first cache storage, a second cache storage, a cache controller coupled to the first cache storage and the second cache storage and operable to receive a memory operation that specifies an address, determine, based on the address, that the memory operation evicts a first set of data from the first cache storage, determine that the first set of data is unmodified relative to an extended memory, and cause the first set of data to be stored in the second cache storage.

A method and processing device for accessing data is provided. The processing device comprises a cache and a processor. The cache comprises a first data section having a first cache hit latency and a second data section having a second cache hit latency that is different from the first cache hit latency of the first data section. The processor is configured to request access to data in memory, the data corresponding to a memory address which includes an identifier that identifies the first data section of the cache. The processor is also configured to load the requested data, determined to be located in the first data section of the cache, according to the first cache hit latency of the first data section of the cache.

Described are methods and a system for atomic memory operations with contended cache lines. A processing system includes at least two cores, each core having a local cache, and a lower level cache in communication with each local cache. One local cache configured to request a cache line to execute an atomic memory operation (AMO) instruction, receive the cache line via the lower level cache, receive a probe downgrade due to other local cache requesting the cache line prior to execution of the AMO, and send the AMO instruction to the lower level cache for remote execution in response to the probe downgrade.

A technique for using a caching layer for key-value storage in a database is described. In one example of the present disclosure, a system can receive, at an unsorted data structure of a caching layer, a key-value pair associated with a data object. The unsorted data structure can store a first plurality of key-value pairs. The system can receive one or more operations for updating the key-value pair in the caching layer. The system can determine the key-value pair is to be migrated to a sorted memory table based on a caching algorithm. The system can migrate the key-value pair to a sorted memory table configured to store a second plurality of key-value pairs that is larger than the first plurality of key-value pairs and sort the key-value pair with the second plurality of key-value pairs prior to storing the key-value pair in the sorted memory table.

A nonvolatile memory device includes a nonvolatile memory, a volatile memory being a cache memory of the nonvolatile memory, and a first controller configured to control the nonvolatile memory. The nonvolatile memory device further includes a second controller configured to receive a device write command and an address, and transmit, to the volatile memory through a first bus, a first read command and the address and a first write command and the address sequentially, and transmit a second write command and the address to the first controller through a second bus, in response to the reception of the device write command and the address.

Computing architecture comprises an off-chip memory, an on-chip cache unit, a prefetching unit, a global scheduler, a transmitting unit, a pre-recombination network, a post-recombination network, a main computing array, a write-back cache unit, a data dependence controller and an auxiliary computing array. The architecture reads data tiles into an on-chip cache in a prefetching mode, and performs computing according to the data tiles; in the computing process of the tiles, a tile exchange network is adopted to recombine a data structure, and a data dependence module is arranged to process a data dependence relationship possibly existing between different tiles. According to the computing architecture, the data utilization rate can be increased, the data processing flexibility is improved, and therefore Cache Miss is reduced, and the memory bandwidth pressure is reduced.

Wavefront loading in a processor is managed and includes monitoring a selected wavefront of a set of wavefronts. Reuse of memory access requests for the selected wavefront is counted. A cache hit rate in one or more caches of the processor is determined based on the counted reuse. Based on the cache hit rate, subsequent memory requests of other wavefronts of the set of wavefronts are modified by including a type of reuse of cache lines in requests to the caches. In the caches, storage of data in the caches is based on the type of reuse indicated by the subsequent memory access requests. Reused cache lines are protected by preventing cache line contents from being replaced by another cache line for a duration of processing the set of wavefronts. Caches are bypassed when streaming access requests are made.

An information processing apparatus including a plurality of groups, each group including a first memory, a second memory different in process speed from the first memory, and a processor including a memory controller that is connected to the first memory and the second memory and that controls an access from a process to the first memory and the second memory, wherein a first processor among a plurality of the processors of the plurality of groups is configured to determine, based on a characteristic of a plurality of the processes accessing data stored in the first memory or the second memory in each of the plurality of groups, an allocation of the plurality of processes onto the plurality of processors.