A system and method improve caching efficiency in a data storage system by performing machine learning processes on metadata relating to extents of data blocks, rather than individual blocks themselves. Thus, once the storage devices are divided into extents, various metadata regarding access to the blocks within each extent are aggregated, and per-extent features are extracted. These features are used to train a data regression model that is subsequently used to infer a most likely “hotness” value for each extent at a future time. These predicted values, which may be further classified as e.g. “hot”, “warm”, and “cold” using thresholds, are used to implement the cache replacement policy. Embodiments scale to large and multi-layered caches, and may avoid common caching problems like thrashing, by adjusting the extent size. Policy goal functions may be optimized by dynamically adjusting the classification thresholds.

A memory device includes a memory array configured with a plurality of memory planes, and control logic, operatively coupled with the memory array. The control logic receives, from a requestor, a plurality of cache read commands requesting first data from the memory array spread across the plurality of memory planes and receives, from the requestor, a cache read context switch command and a snap read command requesting second data from one of the plurality of memory planes of the memory array. Responsive to receiving the cache read context switch command, the control logic suspends processing of the plurality of cache read commands and processes the snap read command to read the second data from the memory array and return the second data to the requestor.

A system and a method to allocate data to a first cache increments a first counter if a reuse indicator for the data indicates that the data is likely to be reused and decremented the counter if the reuse indicator for the data indicates that the data is likely not to be reused. A second counter is incremented upon eviction of the data from the second cache, which is a higher level cache than the first cache. The data is allocated to the first cache if the value of the first counter is equal to or greater than the first predetermined threshold or the value of the second counter equals zero, and the data is bypassed from the first cache if the value of the first counter is less than the first predetermined threshold and the value of the second counter is not equal to zero.

A technique includes, in response to a cache miss occurring with a given processing node of a plurality of processing nodes, using a directory-based coherence system for the plurality of processing nodes to regulate snooping of an address that is associated with the cache miss. Using the directory-based coherence system to regulate whether the address is included in a snooping domain is based at least in part on a number of cache misses associated with the address.

A method for stream-processing biomedical data includes registering, by a file system, with an operating system kernel of the computing device, as a file handler for files requested from a file system mount directory. The file system receives a first request for access to at least a first portion of a file stored on a remotely located storage device and receives a second request for access to at least a second portion of the file. The file system forwards the first request and the second request to a pre-fetching component, which determines whether the first request and the second request are associated with a sequential read operation. The pre-fetching component automatically retrieves a third portion of the requested file, before receiving a third request for the file, based on a determination that the first request and the second request are associated with the sequential read operation.

A system includes a first memory device having a region allocated as a first persistent memory region (PMR) having a first set of pages, a second memory device comprising a non-volatile memory device having a region allocated as a second PMR region having a second set of pages, and at least one processing device, operatively coupled to the first memory device and the second memory device, to implement a PMR mechanism to cause the second PMR region to be accessible through the first PMR region.

Provided is a resource manager. The resource manager may be a memory manager which is configured to determine a plurality of eviction rankings, wherein each of the plurality of eviction rankings assigns a position within the eviction ranking to each of a plurality of eviction candidates based on at least one eviction criterion. The memory manager may then select one of said eviction candidates by applying a voting algorithm to the plurality of eviction rankings and cause the selected eviction candidate to be evicted.

Described apparatuses and methods order memory address portions advantageously for cache-memory addressing. An address bus can have a smaller width than a memory address. The multiple bits of the memory address can be separated into most-significant bits (MSB) and least-significant bits (LSB) portions. The LSB portion is provided to a cache first. The cache can process the LSB portion before the MSB portion is received. The cache can use index bits of the LSB portion to index into an array of memory cells and identify multiple corresponding tags. The cache can also check the corresponding tags against lower tag bits of the LSB portion. A partial match may be labeled as a predicted hit, and a partial miss may be labeled as an actual miss, which can initiate a data fetch. With the remaining tag bits from the MSB portion, the cache can confirm or refute the predicted hit.

An apparatus comprises a cache to store information, items of information in the cache being associated with addresses; cache lookup circuitry to perform lookups in the cache; and a prefetcher to prefetch items of information into the cache in advance of an access request being received for said items of information. The prefetcher selects addresses to train the prefetcher. In response to determining that a cache lookup specifying a given address has resulted in a hit and determining that a cache lookup previously performed in response to a prefetch request issued by the prefetcher for the given address resulted in a hit, the prefetcher selects the given address as an address to be used to train the prefetcher.

A method includes allocating, via a tier allocation component, a first portion of data to a first tier memory component and writing the first portion of data to the first tier memory component in response to a first tier free list having an available entry. The method further includes evicting a second portion of data from the first tier memory component in response to the first tier free list being empty when the first portion of data is allocated to the first tier memory component and writing the first portion of data to the first tier memory component in response to evicting the second portion of data.