Example implementations disclosed herein include techniques for a ready only bufferpool for use in local nodes of a multi-node computing system. Read only transactions executed by a processor can reference a ready only bufferpool resident in a VRAM on the same node. If the desired data page is in the bufferpool the transaction can immediately read data records from the cached data pages. If the desired data page is not in the bufferpool, then the transaction can cause a copy of a corresponding data page in a secondary memory to be installed in the bufferpool. The bufferpool can include more than one copy of a data page simultaneously to handle and prevent cache line misses. Data page are dropped from the bufferpool based on an incrementing per data page counter.

A file server apparatus includes a second file system volume including cache data of a first file system volume stored in a shared file storage apparatus. The file server apparatus determines the operation type indicated by an access request to the first file system volume from a client. When the operation type is directory operation, the file server sends an instruction of directory operation to the shared file storage apparatus, and then transmits a completion response to the client. When the operation type is file operation, the file server apparatus executes a file operation in the second file system volume, transmits a completion response to the client, and then transmits a file operation instruction to the shared file storage apparatus.

Provided are a computer program product, system, and method for adjusting active cache size based on cache usage. An active cache in at least one memory device caches tracks in a storage during computer system operations. An inactive cache in the at least one memory device is not available to cache tracks in the storage during the computer system operations. During caching operations in the active cache, information is gathered on cache hits to the active cache and cache hits that would occur if the inactive cache was available to cache data during the computer system operations. The gathered information is used to determine whether to configure a portion of the inactive cache as part of the active cache for use during the computer system operations.

According to one embodiment, when receiving a write request to designate a first block number and a first logical address from a host, a memory system determines a first location in a first block having the first block number, to which data from the host is to be written, and writes the data from the host to the first location of the first block. The memory system updates a first address translation table managing mapping between logical addresses and in-block physical addresses of the first block, and maps a first in-block physical address indicative of the first location to the first logical address.

Some examples describe data locality solutions for a hyperconverged computing system. In an example, a data request may be received at a Virtual Storage Appliance (VSA) node amongst a plurality of VSA nodes in a hyperconverged computing system. A determination may be made whether a remapped logical block address (LBA) associated with the data request is included on a first mapping layer on the VSA node. In response to a determination that the remapped LBA associated with the data request is present on the first mapping layer of the VSA node, the remapped LBA may be used to resolve the data request. In response to a determination that the remapped LBA associated with another data request is not present on the first mapping layer of the VSA node, a second mapping layer on the VSA node may be used to resolve the other data request.

An apparatus includes an extended capability register and an input/output (I/O) memory management circuitry. The I/O memory management circuitry is to receive, from an I/O device, an address translation request referencing a guest virtual address associated with a guest virtual address space of a virtual machine. The I/O memory management circuitry may translate the guest virtual address to a guest physical address associated with a guest physical address space of the virtual machine, and, responsive to determining that a value stored by the extended capability register indicates a restrict-translation-request-response (RTRR) mode, transmit, to the I/O device, a translation response having the guest physical address.

N-way associative cache pools can be implemented in an N-way associative cache. Different cache pools can be indicated by pool values. Different processes running on a computer can use different cache pools. An N-way associative cache circuit can be configured to have one or more stripe mode cache pools that are N-way associative. A cache control circuit can receive a physical address for a memory location and can interpret the physical address as fields including a tag field that contains a tag value and a set field that contains a set value. The physical address can also be used to determine a pool value that identifies one of the stripe mode cache pools. A set of N cache entries in the one of the stripe mode cache pools can be concurrently searched for the tag value. The set of N cache entries is determined using the set value.

One embodiment provides for a heterogeneous computing device comprising a first processor coupled with a second processor, wherein one or more of the first or second processor includes graphics processing logic; wherein each of the first processor and the second processor includes first logic to perform virtual to physical memory address translation; and wherein the first logic includes cache coherency state for a block of memory associated with a virtual memory address.

A memory system includes a nonvolatile memory and a controller. The nonvolatile memory has first regions in which data writes and data reads can be executed in parallel. Each of the first regions has second regions which are each a data write/read unit. The controller acquires first values indicating a data write load for each of the first regions, detects a first region having a first value greater than or equal to a first threshold, acquires second values indicating a data write load for each of the plurality of second regions in the detected first region, detects a second region having a second value greater than or equal to a second threshold but less than or equal to a third threshold that is higher than the second threshold, and then move data from the detected second region to a second region in another first region.

Described herein is a graphics processing unit (GPU) comprising a first processing cluster to perform parallel processing operations, the parallel processing operations including a ray tracing operation and a matrix multiply operation; and a second processing cluster coupled to the first processing cluster, wherein the first processing cluster includes a floating-point unit to perform floating point operations, the floating-point unit is configured to process an instruction using a bfloat16 (BF16) format with a multiplier to multiply second and third source operands while an accumulator adds a first source operand with output from the multiplier.