A processing device of a memory sub-system is configured to receive a request to add content to a system data structure, wherein a first plurality of blocks of a common pool of blocks are allocated to the system data structure and a second plurality of blocks of the common pool of blocks are allocated to user data; determine whether user data has been written to the second plurality of blocks of the common pool of blocks within a threshold amount of time; and responsive to determining that the user data has not been written to the second plurality of blocks within the threshold amount of time, allocate a block from the second plurality of blocks of the common pool of blocks allocated to user data to the first plurality of blocks of the common pool of blocks allocated for the system data structure.

A memory system includes a first memory device including a plurality of first physical blocks; a second memory device including a plurality of second physical blocks; a first core suitable for managing a plurality of first super blocks that store data associated with a first logical address, the plurality of first super blocks being mapped to the plurality of first physical blocks; a second core suitable for managing a plurality of second super blocks that store data associated with a second logical address, the plurality of second super blocks being mapped to the plurality of second physical blocks; a global wear-leveling manager suitable for changing mapping between the first physical blocks, which are mapped to one among the first super blocks, and the second physical blocks, which are mapped to one among the second super blocks based on degrees of wear of the first and second super blocks.

A method for provided use in a storage device having a controller, the method comprising: identifying, by the controller, a plurality of logical regions in the storage device; obtaining, by the controller, a respective usage metric for each of the logical regions; updating, by the controller, a translation data structure of the storage device, the translation data structure being updated to map any of the logical regions of the storage device to a respective physical portion of the storage device, the respective physical portion being selected based on the respective usage metric of the logical region, wherein the translation data structure is part of a flash translation layer of the storage device, and the translation data structure is configured to store mapping information between a logical address space of the storage device and a physical address space of the storage device.

A respective write cycle count for each of a plurality of data units of a memory device is obtained. Based on the respective write cycle count, whether a data unit of the plurality of data units satisfies a media management criterion is determined. Responsive to determining that the respective write cycle count satisfies the media management criterion, a media management operation every first constant cycle count on the data unit is performed. Responsive to determining that the respective write cycle count does not satisfy the media management criterion, a media management operation every second constant cycle count on the data unit is performed. The second constant cycle count is less than the first constant count.

The present disclosure includes apparatuses and methods for proactive corrective actions in memory based on a probabilistic data structure. A number of embodiments include a memory, and circuitry configured to input information associated with a subset of data stored in the memory into a probabilistic data structure and proactively determine, at least partially using the probabilistic data structure, whether to take a corrective action on the subset of data stored in the memory.

Apparatus, media, methods, and systems for data storage systems and methods for autonomously adapting data storage system performance, lifetime, capacity and/or operational requirements. A data storage system may comprise a controller and one or more non-volatile memory devices. The controller is configured to determine a category for a workload of one or more operations being processed by the data storage system using a machine-learned model. The controller is configured to determine an expected degradation of the one or more non-volatile memory devices. The controller is configured to adjust, based on the expected degradation and an actual usage of physical storage of the data storage system by a host system, an amount of physical storage of the data storage system available to the host system.

Embodiments of the present disclosure relate to a memory system, a memory controller, and a method of operating the same, and more particularly, to a memory system, a memory controller, and a method of operating the same, which calculate a read-attribute value, a write-attribute value, and a time-attribute value for a nonvolatile memory set and determine an operation mode of the nonvolatile memory set on the basis of at least one of the read-attribute value, the write-attribute value, and the time-attribute value, thereby enabling a host to predict whether or not a memory controller executes a background operation.

A descrambler receives data from a memory device. The descrambler calculates a sub-syndrome weight for multiple bits in each of the plurality of descrambled sequences using a set parity check matrix to generate multiple sub-syndrome weights, one for each of the plurality of descrambled sequences. The descrambler selects a sub-syndrome weight among the multiple sub-syndrome weights. The descrambler determines, as a correct scrambler sequence for descrambling the data, a scrambler sequence corresponding to the selected sub-syndrome weight, among the plurality of scrambler sequences.

A memory sub-system periodically performs a first wear leveling operation using a direct mapping function on a data management unit of a memory component in the memory sub-system at a first frequency. The memory sub-system further periodically performs a second wear leveling operation using indirect mapping on a group of data management units of the memory component at a second frequency, wherein the second wear leveling operation is performed less frequently than the first wear leveling operation.

Provided are a computer program product, system, and method for maintaining data structures in a virtual memory comprised of a plurality of heterogeneous memory devices. Access counts are maintained for a plurality of data structures stored in a first level memory device. A determination is made of data structures in the first level memory device having lowest access counts. The determined data structures are deleted from the first level memory device and retaining copies of the data structures in a second level memory device, wherein the first level memory device has lower latency than the second level memory device.