Patent classifications
G06F2212/1044
COMPRESSION AWARE PREFETCH
Methods, devices, and systems for prefetching data. First data is loaded from a first memory location. The first data in cached in a cache memory. Other data is prefetched to the cache memory based on a compression of the first data and a compression of the other data. In some implementations, the compression of the first data and the compression of the other data are determined based on metadata associated with the first data and metadata associated with the other data. In some implementations, the other data is prefetched to the cache memory based on a total of a compressed size of the first data and a compressed size of the other data being less than a threshold size. In some implementations, the other data is not prefetched to the cache memory based on the other data being uncompressed.
Processing host write transactions using a non-volatile memory express controller memory manager
Embodiments of the present disclosure generally relate to an NVMe storage device having a controller memory manager and a method of accessing an NVMe storage device having a controller memory manager. In one embodiment, a storage device comprises a non-volatile memory, a volatile memory, and a controller memory manager. The controller memory manager is operable to store one or more NVMe data structures within the non-volatile memory and the volatile memory.
METHOD AND SYSTEM FOR MANAGING MEMORY LEAKS IN A LINEAR MEMORY MODEL
A method for managing memory leaks in a memory device includes grouping, by a garbage collection system, a plurality of similar memory allocations of the memory device into one or more Unique Fixed Identifiers (UFIs); identifying, by the garbage collection system, one of the one or more UFIs having a highest accumulated memory size and adding each of the plurality of memory allocations in the identified one of the one or more UFIs into a Potential Leak Candidate List (PLCL); identifying, by the garbage collection system, the memory leaks in the memory device by identifying unreferenced memory addresses associated with the plurality of memory allocations in the PLCL; and releasing, by the garbage collection system, the identified unreferenced memory addresses associated with the plurality of memory allocations corresponding to the memory leaks into the memory device.
High performance space efficient distributed storage
High performance space efficient distributed storage is disclosed. For example, a distributed storage volume (DSV) is deployed on a plurality of hosts, with a first host storing a local cache, and a storage controller executing on a processor of the first host receives a request to store a first file. The first file is stored to the local cache. The DSV is queried to determine whether a second file that is a copy of the first file is stored in the DSV. In response to determining that the DSV lacks the second file, the first file is transferred from the local cache to the DSV and then replicated to a second host of the plurality of hosts. In response to determining that the second file resides in the DSV, a reference to the second file is stored in the DSV and then replicated to the second host.
Compiling application with multiple function implementations for garbage collection
Functions of an application may include multiple implementations that have corresponding behaviors but perform different garbage collection-related activities such that the different implementations may be executed during different garbage collection phases to reduce overall garbage collection overhead during application execution.
Dynamically adjusted garbage collection workload
Devices and techniques for a dynamically adjusting a garbage collection workload are described herein. For example, memory device idle times can be recorded. From these recorded idle times, a metric can be derived. A current garbage collection workload can be divided into portions based on the metric. Then, a first portion of the divided garbage collection workload can be performed at a next idle time.
Zone-aware memory management in memory subsystems
Disclosed is a system including a memory device having a plurality of physical memory blocks and associated with a logical address space that comprises a plurality of zones, wherein each zone comprises a plurality of logical block addresses (LBAs), and a processing device, operatively coupled with the memory device, to perform operations of receiving a request to store data referenced by an LBA associated with a first zone of the plurality of zones, obtaining a version identifier of the first zone, obtaining erase values for a plurality of available physical memory blocks of the memory device, selecting, in view of the version identifier of the first zone and the erase values, a first physical memory block of the plurality of available physical memory blocks, mapping a next available LBA within the first zone to the first physical memory block, and storing the data in the first physical memory block.
Technologies for assigning workloads to balance multiple resource allocation objectives
Technologies for allocating resources of managed nodes to workloads to balance multiple resource allocation objectives include an orchestrator server to receive resource allocation objective data indicative of multiple resource allocation objectives to be satisfied. The orchestrator server is additionally to determine an initial assignment of a set of workloads among the managed nodes and receive telemetry data from the managed nodes. The orchestrator server is further to determine, as a function of the telemetry data and the resource allocation objective data, an adjustment to the assignment of the workloads to increase an achievement of at least one of the resource allocation objectives without decreasing an achievement of another of the resource allocation objectives, and apply the adjustments to the assignments of the workloads among the managed nodes as the workloads are performed. Other embodiments are also described and claimed.
Memory system and method for controlling nonvolatile memory
According to one embodiment, a memory system manages a plurality of management tables corresponding to a plurality of first blocks in a nonvolatile memory. Each management table includes a plurality of reference counts corresponding to a plurality of data in a corresponding first block. The memory system copies a set of data included in a copy-source block for garbage collection and corresponding respectively to reference counts belonging to a first reference count range to a first copy-destination block, and copies a set of data included in the copy-source block and corresponding respectively to reference counts belonging to a second reference count range having a lower limit higher than an upper limit of the first reference count range to a second copy-destination block.
System and method of using persistent memory to support small-sized data append for object store
A system and a method are disclosed that efficiently supports an append operation in an object storage system. A size of data received with a request for an append operation from an application is determined based on a data-alignment characteristic of a storage medium. Data that is not aligned with the data-alignment characteristic is stored in persistent memory and aggregated with other data from the application that is not aligned with the data-alignment characteristic, while data that is aligned with the data-alignment characteristic is stored directly in the storage medium. Aggregated data that becomes aligned with the data-alignment characteristic as additional requests for append operations are received are migrated to the storage medium.