Technologies for media management for column-based memory systems include a memory controller including an indirection table. The memory controller receives a memory access to a column-addressable memory indicative of a memory row address. The memory controller determines a logical sub-block identifier based on the memory row address and looks up a physical sub-block identifier in the indirection table. The memory controller issues a redirected memory access indicative of the physical sub-block identifier to the column-addressable memory. The memory access may include a column read. The memory controller may perform a media management operation by copying or moving data from a source physical sub-block to a destination physical sub-block. The memory controller updates the indirection table with the destination physical sub-block for the associated logical sub-block identifier. Other embodiments are described and claimed.

Provided are a computer program product, system, and method for maintaining data structures in a virtual memory comprised of a plurality of heterogeneous memory devices. Access counts are maintained for a plurality of data structures stored in a first level memory device. A determination is made of data structures in the first level memory device having lowest access counts. The determined data structures are deleted from the first level memory device and retaining copies of the data structures in a second level memory device, wherein the first level memory device has lower latency than the second level memory device.

Disclosed herein are techniques for management of a non-volatile memory device. In one example, an integrated circuit comprises a cache device and a management controller. The cache device is configured to store a first mapping between logical addresses and physical addresses of a first memory, the first mapping being a subset of mapping between logical addresses and physical addresses of the first memory stored in a second memory, and an access count associated with each of the physical addresses of the first mapping. The management controller is configured to: maintain access statistics of the first memory based on the access counts stored in the cache device; and determine the mapping between logical addresses and physical addresses stored in the second memory based on the access statistics and predicted likelihoods of at least some of the logical addresses receiving an access operation.

The present invention provides a control method of a server, wherein the server includes a write buffer for temporarily storing data from an electronic device, the write buffer has a plurality of sectors, and the write buffer has a write pointer and a flush pointer; and the control method comprises: setting each sector to have one of a plurality of states comprising an empty state, a merging state, a need-flush state and a flushing state; and referring to a state of a specific sector indicted by the write pointer to determine if ignoring the specific sector to directly process a sector after the specific sector.

A processor may boot a system. The processor may determine a type of operation of data based on an application tag. The processor may analyze at least one specific table for the application tag. The processor may perform an operation associated with the application tag.

A method for rebuilding data when changing erase block sizes in a storage system is provided. The method includes determining one or more erase blocks to be rebuilt and allocating one or more replacement erase blocks, wherein the one or more erase blocks and the one or more replacement erase blocks have differing erase block sizes. The method includes mapping logical addresses, for the one or more erase blocks, to the one or more replacement erase blocks and rebuilding the one or more erase blocks into the one or more replacement erase blocks, in accordance with the mapping.

A method to perform an on demand refresh operation of a memory sub-system is disclosed. The method includes identifying a temporal attribute of user data stored in the memory component, upon determining that the identified temporal attribute satisfies a time condition, providing an indication whether a refresh operation of the user data improves performance of the memory component, receiving an indication to perform the refresh operation of the memory component, and responsive to a time between the refresh operation and a previously performed refresh operation not satisfying a threshold criterion, refraining from performing the refresh operation of the memory component.

A system and method is disclosed for managing data in a non-volatile memory. The system may include a non-volatile memory having multiple non-volatile memory sub-drives. A controller of the memory system is configured to route incoming host data to a desired sub-drive, keep data within the same sub-drive as its source during a garbage collection operation, and re-map data between sub-drives, separate from any garbage collection operation, when a sub-drive overflows its designated amount logical address space. The method may include initial data sorting of host writes into sub-drives based on any number of hot/cold sorting functions. In one implementation, the initial host write data sorting may be based on a host list of recently written blocks for each sub-drive and a second write to a logical address encompassed by the list may trigger routing the host write to a hotter sub-drive than the current sub-drive.

A Solid State Drive (SSD) is disclosed. The SSD may include flash memory to store data. An SSD controller may manage reading and writing data to the flash memory. The SSD may include an automatic stream detection logic to select a stream identifier responsive to attributes of data. A garbage collection logic may select an erase block and program valid data in the erase block into a second block responsive to a stream ID determined the automatic stream detection logic. The stream ID may be determined after the garbage collection logic has selected the erase block for garbage collection.

A virtualized system includes a nonvolatile memory device, a processing circuitry configured to provide a virtualization environment, implement a plurality of virtual units and implement a virtual unit manager. The virtual units operate independently of each other in the virtualization environment and perform a flash translation layer operation inside the virtual units. The flash translation layer operation includes converting a logical block address associated with a storage access operation of the nonvolatile memory device to a physical block address of the nonvolatile memory device. The virtual unit manager controls the virtual units in the virtualization environment.