A method for facilitating recovery from a crash of a solid-state storage device (SSD) is adapted to be implemented by an SSD controller of the SSD that receives a write request. The method includes: assigning a write request identifier (WID) and a request size in a spare area of each written page of the SSD; counting a number of appearances of the WID in all written page(s) to result in a WID count; determining whether the WID count is equal to the request size; and determining that the write request is completed and is eligible for recovery after a crash of the SSD when it is determined that the WID count is equal to the request size.

According to one embodiment, in a memory system, a controller is configured to write first data in a page in a block in response to a write request from a host, and update second information used to manage a correspondence between a logical address designated by the write request and a second physical address which is a storage location in the first memory. The controller is configured to perform a first process of updating the first information with the second information and storing the updated information in the first memory. The controller is configured to acquire the first physical address associated to a logical address designated by the write request from the first information. The controller is configured to store, in the first memory, third information including information in which the acquired first physical address and the second physical address are associated.

Systems, apparatuses and methods may provide for technology that reads a lower page, one or more intermediate pages and a last page from a set of multi-level non-volatile memory (NVM) cells, wherein one or more of a lower read time associated with the lower page or a last read time associated with the last page is substantially similar to an intermediate read time associated with the one or more intermediate pages.

A method, non-transitory computer readable medium and storage controller computing device that receives a read request from a client device. Data corresponding to the read request is retrieved from a flash cache comprising local flash memory. The data is returned to the client device in response to the read request. A determination is made when the data is stored in a flash pool. The flash pool comprises a plurality of solid state drives (SSDs). The data is inserted into the flash pool, when the determining indicates that the data is not stored in the flash pool. With this technology, a flash pool is populated based on hits in a flash cache. Accordingly, flash cache is utilized to provide low latency reads while the most important data is preserved in the flash pool to be used by another storage controller computing device in the event of a failover.

This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to “plan ahead” in a manner supporting host issuance of true multi-plane read commands.

At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.

Techniques are disclosed relating to storing translations in memory that are usable to access data on a recording medium. In one embodiment, a request is sent for a memory allocation within a non-pageable portion of a memory in a computer system. Responsive to the request, allocated memory is received. Translations usable to map logical addresses to physical addresses within a storage device are stored within the allocated memory. In some embodiments, the translations are usable to access an area within the storage device used to store pages evicted from the memory. In one embodiment, a size of the memory allocation is determined based on a size of the area. In another embodiment, a size of the memory allocation is determined based on a size of a partition including the area. In some embodiments, the storage device is a solid-state storage array.

A data erasing method and apparatus applied to a flash memory. The method includes receiving a data erasing instruction, where the data erasing instruction instructs to erase data or at least one data section of data sections corresponding to data, when the data erasing instruction instructs to erase the data, searching for recorded storage addresses of all the data sections corresponding to the data, and erasing all the data sections corresponding to the data according to the storage addresses that are found; and when the data erasing instruction instructs to erase the at least one data section of the data sections corresponding to the data, searching for a recorded storage address of the at least one data section, and erasing the at least one data section according to the storage address that is found. The data erasing method and apparatus may be used in an implementation technology of the flash memory.

Technologies are generally described herein to detect non-volatile write request sequences. A write request is received to write to a solid-state device that includes the non-volatile memory. A determination is made as to whether the write request is part of a non-volatile write request sequence or is not pan of the non-volatile write request sequence, in response to determining that the write request is part of the non-volatile write request sequence, the write request is associated with the non-volatile write request sequence. In response to determining that the write request is not part of the non-volatile write request sequence, the data associated with the write request is written to a cache that is coupled to the non-volatile memory. The data associated with the non-volatile write request sequences may be written directly to the non-volatile memory.

A storage apparatus managing method applied to a first storage apparatus and a second storage apparatus coupled to the electronic apparatus is disclosed. The first storage apparatus includes a local registering region and a global registering region. The storage apparatus managing method includes: when the global registering region does not have a target data unit, reading the target data unit from the local registering region or from the second storage apparatus; and copying the target data unit to the global registering region. When the target data unit is copied to the global registering region, the target data unit is copied to a global registering buffer region, or otherwise in response to the global registering buffer region not having enough space, the target data unit is copied to a global registering file region.