A semiconductor device includes a resistance variable element including a free magnetic layer, a tunnel barrier layer and a pinned magnetic layer; and a magnetic correction layer disposed over the resistance variable element to be separated from the resistance variable element, and having a magnetization direction which is opposite to a magnetization direction of the pinned magnetic layer.

The present invention is directed to a magnetic memory device that emulates DRAM and provides a plug-in or drop-in replacement for DRAM. The memory device includes one or more magnetic memory banks for storing data; a controller configured to issue a dormant write command upon receiving a refresh command for recharging DRAM capacitors; and a memory cache for storing temporary data and configured to save the temporary data to the one or more magnetic memory banks upon receiving the dormant write command from the controller. The memory device may be compliant with at least one version of low power DDR (LPDDR) Specification or at least one version of DDR SDRAM Specification.

Providing for a memory apparatus configured for improved data management for a two-terminal memory array is described herein. By way of example, disclosed embodiments relate to page management and transfer of data between page-sized subsets of a page buffer, and respective pages within one or more memory banks of the two-terminal memory array. The memory apparatus can emulate a larger page size than a physical page buffer utilized by the memory apparatus, to provide compatibility with different page size defaults while lowering current consumption by the page buffer. This can facilitate large or small array operations, taking advantage of higher efficiencies of two-terminal memory devices. In addition, page buffer data management can facilitate interleaved data transfers among multiple banks of memory, facilitating large memory capacities for a disclosed memory apparatus.

Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: an interlayer dielectric layer formed over a substrate and having a contact hole; a contact plug formed in a lower part of the contact hole; a contact pad formed in an upper part of the contact hole; an amorphous buffer layer interposed between the contact plug and the contact pad; and a variable resistance element formed over the contact pad.

A memory access command, column address and plurality of write data values are received within an integrated-circuit memory chip via external signaling links. In response to the memory access command, the integrated-circuit memory chip (i) decodes the column address to select address-specified sense amplifiers from among a plurality of sense amplifiers that constitute a sense amplifier bank, (ii) reads first data, constituted by a plurality of read data values, out of the address-specified sense amplifiers, and (iii) overwrites the first data within the address-specified sense amplifiers with second data constituted by one or more of the write data values and by one or more of the read data values.

A microcomputer comprising a microprocessor unit and a first memory unit is disclosed. In one aspect, the microprocessor unit comprises at least one functional unit and at least one register. Further, the at least one register is a wide register comprising a plurality of second memory units which are capable to each contain one word, the wide register being adapted so that the second memory units are simultaneously accessible by the first memory unit, and at least part of the second memory units are separately accessible by the at least one functional unit. Further, the first memory unit is an embedded non-volatile memory unit.

A data erasing method and apparatus applied to a flash memory. The method includes receiving a data erasing instruction, where the data erasing instruction instructs to erase data or at least one data section of data sections corresponding to data, when the data erasing instruction instructs to erase the data, searching for recorded storage addresses of all the data sections corresponding to the data, and erasing all the data sections corresponding to the data according to the storage addresses that are found; and when the data erasing instruction instructs to erase the at least one data section of the data sections corresponding to the data, searching for a recorded storage address of the at least one data section, and erasing the at least one data section according to the storage address that is found.

A method and a storage system are provided for implementing enhanced solid state storage class memory (eSCM) including a direct attached dual in line memory (DIMM) card containing Dynamic Random Access Memory (DRAM), and at least one 5 non-volatile memory, for example, Phase Change Memory (PCM), Resistive RAM (ReRAM), Spin-Transfer-Torque RAM (STT-RAM), and NAND Flash chips. An eSCM processor controls selectively allocating data among the DRAM, and the at least one non-volatile memory primarily based upon a data set size.

This technology provides an electronic device and a method for fabricating the same. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes a Magnetic Tunnel Junction (MTJ) structure including a free layer having a variable magnetization direction, a pinned layer having a pinned magnetization direction, and a tunnel barrier layer interposed between the pinned layer and the free layer; a magnetic correction layer located under the MTJ structure and operates to reduce an influence of a stray magnetic field generated by the pinned layer; and an under layer located under the magnetic correction layer and including a metal oxide layer.

An electronic device includes a semiconductor memory device. The semiconductor memory device includes: a word line driving unit for driving a plurality of word lines; a first circuit area including a first cell array arranged at one side of the word line driving unit; a second circuit area including a second cell array arranged at the other side of the word line driving unit; a bias voltage generation unit arranged between the first cell array and the second cell array; a first read control unit; and a second read control unit. The first and second cell arrays include storage cells having variable resistance elements, and the bias voltage generation unit generates a bias voltage based on currents flowing through a first reference resistance element included in the first cell array and a second reference resistance element included in the second cell array.