A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol

A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as far memory. Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as near memory.

A method and/or system for providing for write once read many (WORM) times from at least some addresses of a storage drive that is otherwise manufactured for multiple writes to individual addresses. In at least one embodiment, a WORM area(s) is defined by a START_LBA and an END_LBA and the method uses a HWM_LBA to determine whether a LBA in the WORM area has been written to previously and to prevent previously written to LBA(s) in the WORM area from being rewritten. In at least one embodiment where there are multiple WORM areas, each WORM area has its own respective START_LBA, END_LBA and HWM_LBA.

An electronic device including a semiconductor memory may be provided. The semiconductor memory may include a write circuit configured for generating a first current. The semiconductor memory may include a first selection circuit configured for coupling the first write circuit to a first line based on a first selection signal. The semiconductor memory may include a second write circuit configured for generating a second current. The semiconductor memory may include a second selection circuit configured for coupling the second write circuit to a second line based on a second selection signal. The semiconductor memory may include a memory cell coupled between the first line and the second line. The semiconductor memory may include a voltage control circuit configured for controlling a voltage level of the second line.

A method is described that includes deciding to enter a lower power state, and, shutting down a memory channel in a computer system in response where thereafter other memory channels in the computer system remain active so that computer remains operative while the memory channel is shutdown.

Examples of a multi-level memory with direct access are described. Examples include designating an amount of a non-volatile random access memory (NVRAM) for use as memory for a computer system. Examples also include designating a second amount of the NVRAM to for use as storage for the computing device. Examples also include re-designating at least a first portion of the first amount of NVRAM from use as memory to use as storage.

A coherence logic of a first core in a multi-core processor receives a request to send a cache line to a second core in the multi-core processor. In response to receiving the request, the coherence logic determines if the cache line is associated to a logically nonvolatile virtual page mapped to a nonvolatile physical page in a nonvolatile main memory. If so, the coherence logic flushes the cache line from the cache to the nonvolatile main memory and then sends the cache line to the second core.

Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: an interlayer dielectric layer formed over a substrate and having a contact hole; a contact plug formed in a lower part of the contact hole; a contact pad formed in an upper part of the contact hole; an amorphous buffer layer interposed between the contact plug and the contact pad; and a variable resistance element formed over the contact pad.

A vacuum blender having a vessel, a motor base containing a motor having a motor drive shaft, a blade holder having a blade with a blade shaft for engaging the motor drive shaft, and a fan connected to the motor drive shaft. The blender includes a conduit system for the passage of air from the vessel to an area in proximity to the fan before passing to the outside of the motor base. The conduit system is connected to a valve system, preferably including a three way valve or Venturi valve. The fan and blade are capable of being selectively actuated using a gear or clutch system, preferably operated by firmware. The invention is capable of evacuating air from the vessel before blending of the food contents occurs.

Subject matter disclosed herein relates to management of a memory device.