A method, non-transitory computer readable medium, and device that assists with caching filesystem metadata to a partner non-volatile random-access memory (NVRAM) includes caching metadata related to an incoming data modifying operation generated by a client computing device to at least one storage controller device in a cluster. A service interruption event that makes a data block present in the storage device of a hosting storage node inaccessible to the client computing device is determined for during the caching. The requested metadata block from the at least one NVRAM is retrieved when the service interruption event is determined. The cache is warmed using the retrieved metadata block from the at least one NVRAM.

Various embodiments comprise devices to manage multiple memory types and reconfigure partitions in a memory device as directed by a host. In one embodiment, the apparatus is to manage commands through a first interface controller to mapped portions of a first memory not having an attribute enhanced set, and map portions of a second memory having the attribute enhanced set through a second interface controller. Additional devices are described.

Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a vertical electrode formed over a substrate; a plurality of first memory elements and a plurality of first interlayer dielectric layers alternately stacked along a first side surface of the vertical electrode; and a plurality of second memory elements and a plurality of second interlayer dielectric layers alternately stacked along a second side surface of the vertical electrode, and the plurality of first memory elements correspond to the plurality of second interlayer dielectric layers, respectively, in the vertical direction.

A system-on-chip includes a magnetic random access memory and a security interface. The magnetic random access memory includes a plurality of memory areas, each of the plurality of memory areas having a different security level. The security interface circuitry configured to: identify a memory area from among the plurality of memory areas based on a received memory address associated with a received memory command; determine a security level associated with the identified memory area; and perform a memory operation on received data based on the received memory command and the determined security level.

The present invention is directed to a magnetic memory device that emulates DRAM and provides a plug-in or drop-in replacement for DRAM. The memory device includes one or more magnetic memory banks for storing data; a controller configured to issue a dormant write command upon receiving a refresh command for recharging DRAM capacitors; and a memory cache for storing temporary data and configured to save the temporary data to the one or more magnetic memory banks upon receiving the dormant write command from the controller. The memory device may be compliant with at least one version of low power DDR (LPDDR) Specification or at least one version of DDR SDRAM Specification.

A memory access command, column address and plurality of write data values are received within an integrated-circuit memory chip via external signaling links. In response to the memory access command, the integrated-circuit memory chip (i) decodes the column address to select address-specified sense amplifiers from among a plurality of sense amplifiers that constitute a sense amplifier bank, (ii) reads first data, constituted by a plurality of read data values, out of the address-specified sense amplifiers, and (iii) overwrites the first data within the address-specified sense amplifiers with second data constituted by one or more of the write data values and by one or more of the read data values.

A processing system for performing persistent write operations comprises a host and a memory system. The memory system, upon receiving a Persistent Write command and associated write data from the host, performs a Persistent Write of the write data to a non-volatile memory in the memory system based on the Persistent Write command. The memory system may also a receive a write identification (WID) associated with the Persistent Write command from the host and provide, upon successful completion of the Persistent Write, a Persistent Write completion indication along with the associated WID to the host. Persistent Write completion indications may be provided to the host in a different order from an order in which corresponding commands were received. Statuses of Persistent Write commands may be maintained in a completed bitmap or a pending bitmap. A FLUSH command may be provided to indicate that all prior writes buffered in volatile media are to be pushed to non-volatile or persistent memory. The memory system may include a non-volatile dual in-line memory module which supports Persistent Writes (NVDIMM).

A memory access command, column address and plurality of write data values are received within an integrated-circuit memory chip via external signaling links. In response to the memory access command, the integrated-circuit memory chip (i) decodes the column address to select address-specified sense amplifiers from among a plurality of sense amplifiers that constitute a sense amplifier bank, (ii) reads first data, constituted by a plurality of read data values, out of the address-specified sense amplifiers, and (iii) overwrites the first data within the address-specified sense amplifiers with second data constituted by one or more of the write data values and by one or more of the read data values.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for performing topological scheduling on a machine-learning accelerator having an array of tiles. One of the methods includes performing, at each time step of a plurality of time steps corresponding respectively to columns within each of a plurality of wide columns of the tile array, operations comprising: performing respective multiplications using tiles in a respective tile column for the time step, computing a respective output result for each respective tile column for the time step including computing a sum of results of the multiplications for the tile column, and storing the respective output result for the tile column in a particular output RAM having a location within the same tile column and on a row from which the output result will be read by a subsequent layer of the model.

In certain aspects, one or more solid-state storage devices (SSDs) are provided that include a controller and non-volatile memory coupled to the controller. The non-volatile memory can include one or more portions configured as main memory or cache memory. When data stored in the main memory is written to the cache memory for processing, the data in the main memory is erased. In certain aspects, storage systems are provided that include one or more of such SSDs coupled to a host system. In certain aspects, methods are provided that include: receiving, by a first such SSD, a first command to write data to memory; determining that the data is stored in a main memory and is to be written to the cache memory for processing; writing the data to the cache memory; and erasing the data from the main memory.