A method and a processing device are provided for sequentially aggregating data to a write log included in a volume of a random-access medium. When data of a received write request is determined to be suitable for sequentially aggregating to a write log, the data may be written to the write log and a remapping tree, for mapping originally intended destinations on the random-access medium to one or more corresponding entries in the write log, may be maintained and updated. At time periods, a checkpoint may be written to the write log. The checkpoint may include information describing entries of the write log. One or more of the checkpoints may be used to recover the write log, at least partially, after a dirty shutdown. Entries of the write log may be drained to respective originally intended destinations upon an occurrence of one of a number of conditions.

In one form, a computer system includes a central processing unit, a memory controller coupled to the central processing unit and capable of accessing non-volatile random access memory (NVRAM), and an NVRAM-aware operating system. The NVRAM-aware operating system causes the central processing unit to selectively execute selected ones of a plurality of application programs, and is responsive to a predetermined operation to cause the central processing unit to execute a memory persistence procedure using the memory controller to access the NVRAM.

A data storage system, including a host server having storage processors, a PCIe fabric, and a GBE fabric, and two or more data storage modules having a bank of DRAM, long-term storage drives, a host interface, including a PCIe interface and a GBE interface, an application specific integrated circuit connected to the host interface, the storage drives, and the DRAM, and a battery, the battery providing power to the DRAM and SSDs in an event of failure of a main power supply. Data streams transmitted from the host server via a PCIe connection of the PCIe fabric are received at the host interface and placed directly in DRAM as a write-back cache operation. In addition, the battery provides the DRAM with non-volatile memory capabilities and the storage modules with portability. A method for arbitration of write requests between the storage processors of the data storage system is also disclosed.

A tag memory and a cache system with automating tag comparison mechanism and a cache method thereof are provided. The tag memory in the cache system includes a memory cell array, sensing amplifiers and a tag comparison circuit. The memory cell array stores cache tags, and outputs row tags of the cache tags according to an index in a memory address. The sensing amplifiers perform signal amplifications on the row tags to serve as comparison tags. The tag comparison circuit performs parallel comparisons between a target tag in the memory address and the row tags. When one of the row tags matches the target tag, the tag comparison circuit outputs a location of the matched row tag to serve as a first column address. The first column address is a column address where the memory address corresponds to a first data memory in the cache system.

An apparatus is described. The apparatus includes a memory controller comprising logic circuitry to implement a mass storage cache in a non volatile region of a system memory. The non volatile region of the system memory is to support execution of program code directly out of the non volatile region system memory.

Improved techniques for storing data involve storing compressed data in blocks of a first AU size and storing uncompressed data in blocks of a second AU size larger than the first AU size. For example, when a storage processor compresses a chunk of data, the storage processor checks whether the compressed chunk fits in the smaller AU size. If the compressed chunk fits, then the storage processor stores a compressed chunk in a block having the smaller AU size. Otherwise, the storage processor stores the uncompressed chunk in a block having the larger AU size. Advantageously, the improved techniques promote better disk and cache utilization, which improves performance without disrupting block mapping.

A storage controller has a processor, a volatile first cache memory that is coupled to the processor and that temporarily stores data, a nonvolatile second cache memory that is coupled to a microprocessor and that temporarily stores data, and a battery that is configured to supply electrical power to at least the processor and the first cache memory when a power stoppage has occurred. The second cache memory includes a dirty data area for storing dirty data, which is data that is not stored in the storage device, and a remaining area other than the dirty data area. When a power stoppage has occurred, the processor stores as target data in the remaining area of the second cache memory either all or a part of the data stored in the first cache memory.

Apparatus and method for managing a media cache through the monitoring of operational vibration of a data storage device. In some embodiments, a non-volatile media cache of the data storage device is partitioned into at least first and second zones having different data recording characteristics. Input data are received for storage in a non-volatile main memory of the data storage device. An amount of operational vibration associated with the data storage device is measured. The input data are stored in a selected one of the first or second zones of the media cache prior to transfer to the main memory responsive to a comparison of the measured amount of operational vibration to a predetermined operational vibration threshold.