In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.

In one example, a method includes receiving metadata in the form of a modification to metadata represented by a file system namespace abstraction, and the file system namespace abstraction corresponds to less than the entire file system namespace. Next, the file system namespace abstraction is updated based on the received metadata. Next, a determination is made whether or not caching is enabled for the file system namespace abstraction. If caching is enabled for the file system namespace abstraction, the updated file system namespace abstraction is cached in SSD storage.

Provided are techniques for handling cache and Non-Volatile Storage (NVS) out of sync writes. At an end of a write for a cache track of a cache node, a cache node uses cache write statistics for the cache track of the cache node and Non-Volatile Storage (NVS) write statistics for a corresponding NVS track of an NVS node to determine that writes to the cache track and to the corresponding NVS track are out of sync. The cache node sets an out of sync indicator in a cache data control block for the cache track. The cache node sends a message to the NVS node to set an out of sync indicator in an NVS data control block for the corresponding NVS track. The cache node sets the cache track as pinned non-retryable due to the write being out of sync and reports possible data loss to error logs.

A device supporting big data in a process plant includes an interface to a communications network, a cache configured to store data observed by the device, and a multi-processing element processor to cause the data to be cached and transmitted (e.g., streamed) for historization at a unitary, logical centralized data storage area. The data storage area stores multiple types of process control or plant data using a common format. The device time-stamps the cached data, and, in some cases, all data that is generated or created by or received at the device may be cached and/or streamed. The device may be a field device, a controller, an input/output device, a network management device, a user interface device, or a historian device, and the device may be a node of a network supporting big data in the process plant. Multiple devices in the network may support layered or leveled caching of data.

A computer system of a service provider includes a processing unit executing a thread issued by a user and a random access memory (RAM) cache disposed external to the processing unit and operatively coupled to the processing unit to store data accessed or to be accessed by the processing unit. The processing unit includes control circuitry configured to, in response to receiving an access request while the thread is being executed, determine whether the thread is allowed to access the RAM cache according to a service level agreement (SLA) level established between the service provider and the user, and when the thread is RAM cacheable, access the RAM cache.

Examples may include techniques to monitor processing of I/O requests of an application being executed by a computing platform by collecting a trace of the I/O requests, the trace including an I/O class of each I/O request; replay the trace and automatically analyze possible cache configuration policies for using a cache during execution of the application by the computing platform; and determine an optimal cache configuration policy for the cache from the possible cache configuration policies. The optimal cache configuration policy may then be applied to use of the cache during subsequent execution of the application by the computing platform, thereby improving performance.

Embodiments of the present disclosure are directed towards a computer system with cache policy that may be modified in response to temperature changes. In some embodiments, the system may include a memory storage having a first storage device with a first response time, and a second storage device with a second response time that may be higher than the first response time. The system may include a cache policy module to facilitate execution of I/O requests to access the memory storage. The cache policy module may be configured to restrict access to at least a portion of the first storage device and provide access to the second storage device, in response to an increase of temperature of the first storage device above a threshold. Other embodiments may be described and/or claimed.

Embodiments of the present disclosure may relate to a data storage controller that may include a host interface to receive a request from a host to perform a data copy operation on a non-volatile data storage component of a data storage device, where the request identifies one or more source ranges of the non-volatile data storage component from which data is to be copied, a destination range of the non-volatile data storage component to which the data is to be copied, and a transfer length in bytes for each of the one or more source ranges, and a processor coupled with the host interface to process the request from the host to perform the data copy operation to copy the data from the one or more source ranges to the destination range based at least in part on the transfer length in bytes. Other embodiments may be described and/or claimed.

The present disclosure includes memory having a static cache and a dynamic cache. A number of embodiments include a memory, wherein the memory includes a first portion configured to operate as a static single level cell (SLC) cache and a second portion configured to operate as a dynamic SLC cache when the entire first portion of the memory has data stored therein.

A data storage device may consist of a non-volatile memory having rewritable in-place memory cells each with a read-write asymmetry. The non-volatile memory can store boot data that is subsequently loaded by a selection module of the data storage device. The selection module may bypass a memory buffer of the data storage device to load the boot data.