A system and method for providing dynamic I/O virtualization is herein disclosed. According to one embodiment, a device capable of performing hypervisor-agnostic and device-agnostic I/O virtualization includes a host computer interface, memory, I/O devices (GPU, disk, NIC), and efficient communication mechanisms for virtual machines to communicate their intention to perform I/O operations on the device. According to one embodiment, the communication mechanism may use shared memory. According to some embodiments, the device may be implemented purely in hardware, in software, or using a combination of hardware and software. According to some embodiments, the device may share its memory with guest processes to perform optimizations including but not limited to a shared page cache and a shared heap.

Described is storage system and method for reducing power consumption. The storage system has first and second physical disks configured to provide mirroring. The first physical disk is placed into a power-saving mode of operation, while the second physical disk is in an active mode of operation responding to read and write requests. The first physical disk transitions from the power-saving mode of operation to an active mode of operation for destaging writes pending from cache to the first physical disk, while the second physical disk responds to read and write requests. The second physical disk transitions from the active mode of operation to the power-saving mode of operation, while the first physical disk responds to read and write requests.

A method and apparatus are disclosed for providing a DMA process. Accordingly, a DMA process is initiated for moving data from contiguous first locations to contiguous second locations and to a third location or third locations. Within the DMA process the data from each of the contiguous first locations is retrieved and stored in a corresponding one of the contiguous second locations and in the third location or corresponding one of the third locations. The DMA process is performed absent retrieving the same data a second other time prior to storing of same within the corresponding one of the contiguous second locations and in the third location or corresponding one of the third locations.

A computing device having a host memory and a host processor for executing instructions out of the host memory; and a network interface card interfacing with the computing device are provided. When there is a cache hit for a read request, the network interface card processes the read request by obtaining data stored from one or both of the host memory and a storage device that the network interface card accesses without involving the host processor and when there are is a cache miss, then the read request is processed by the host processor.

Provided are a method and apparatus for a memory module to accept a command in multiple parts. A first half of a command is placed on a bus for a memory module in a first clock cycle. A chip select signal is placed on the bus for the memory module for the first half of the command. A second half of the command is placed on the bus in a second clock cycle following the first clock cycle, wherein the memory module accepts the second half of the command a delay interval from accepting the first half of the command.

A system and method for providing dynamic I/O virtualization is herein disclosed. According to one embodiment, a device capable of performing hypervisor-agnostic and device-agnostic I/O virtualization includes a host computer interface, memory, I/O devices (GPU, disk, NIC), and efficient communication mechanisms for virtual machines to communicate their intention to perform I/O operations on the device. According to one embodiment, the communication mechanism may use shared memory. According to some embodiments, the device may be implemented purely in hardware, in software, or using a combination of hardware and software. According to some embodiments, the device may share its memory with guest processes to perform optimizations including but not limited to a shared page cache and a shared heap.

Provided are a method and apparatus for selecting one of a plurality of bus interface configurations to use. Selection is made of a first bus interface configuration having a first bus width to send data over the bus in response to an interface parameter indicating a first interface parameter. Selection is made of a second bus interface configuration having a second bus width to send data over the bus in response to the interface parameter indicating a second interface parameter, wherein the first bus width has fewer bits than the second bus width.

A queuing requester for access to a memory system is provided. Transaction requests are received from two or more requestors for access to the memory system. Each transaction request includes an associated priority value. A request queue of the received transaction requests is formed in the queuing requester. Each transaction request includes an associated priority value. A highest priority value of all pending transaction requests within the request queue is determined. An elevated priority value is selected when the highest priority value is higher than the priority value of an oldest transaction request in the request queue; otherwise the priority value of the oldest transaction request is selected. The oldest transaction request in the request queue with the selected priority value is then provided to the memory system. An arbitration contest with other requesters for access to the memory system is performed using the selected priority value.

A device may receive a direct memory access request that identifies a virtual address. The device may determine whether the virtual address is within a particular range of virtual addresses. The device may selectively perform a first action or a second action based on determining whether the virtual address is within the particular range of virtual addresses. The first action may include causing a first address translation algorithm to be performed to translate the virtual address to a physical address associated with a memory device when the virtual address is not within the particular range of virtual addresses. The second action may include causing a second address translation algorithm to be performed to translate the virtual address to the physical address when the virtual address is within the particular range of virtual addresses. The second address translation algorithm may be different from the first address translation algorithm.

A system and method for providing dynamic I/O virtualization is herein disclosed. According to one embodiment, a device capable of performing hypervisor-agnostic and device-agnostic I/O virtualization includes a host computer interface, memory, I/O devices (GPU, disk, NIC), and efficient communication mechanisms for virtual machines to communicate their intention to perform I/O operations on the device. According to one embodiment, the communication mechanism may use shared memory. According to some embodiments, the device may be implemented purely in hardware, in software, or using a combination of hardware and software. According to some embodiments, the device may share its memory with guest processes to perform optimizations including but not limited to a shared page cache and a shared heap.