Providing for a memory apparatus comprising multiple banks of non-volatile memory and a high-speed data bus is described herein. By way of example, the memory apparatus can employ a standard or near-standard DRAM bus as an interface to high-performance two-terminal memory arrays. Interleaved operation can facilitate throughputs over 2gigabytes/second, in various embodiments, and larger throughputs in at least some embodiments, by interleaving multiple memory banks that are separately addressed via one or more mode registers, referred to as an index register(s). Further, the memory apparatus can have one or two terabytes of total storage, with capacity to increase storage volume. According to various embodiments, the memory apparatus can operate with a standard DRAM controller, or a memory controller configured with a DRAM communication protocol, modified in software or firmware to match configurations of the non-volatile memory employed for the multiple banks of memory.

A system and method for providing dynamic I/O virtualization is herein disclosed. According to one embodiment, a device capable of performing hypervisor-agnostic and device-agnostic I/O virtualization includes a host computer interface, memory, I/O devices (GPU, disk, NIC), and efficient communication mechanisms for virtual machines to communicate their intention to perform I/O operations on the device. According to one embodiment, the communication mechanism may use shared memory. According to some embodiments, the device may be implemented purely in hardware, in software, or using a combination of hardware and software. According to some embodiments, the device may share its memory with guest processes to perform optimizations including but not limited to a shared page cache and a shared heap.

Methods of operating a memory include performing a memory access operation, obtaining an address corresponding to a subsequent memory access operation prior to stopping the memory access operation, stopping the memory access operation, sharing charge between access lines used for the memory access operation and access lines to be used for the subsequent memory access operation, and performing the subsequent memory access operation.

Data items to be stored in a queue are received, where the queue is distributed among a plurality of memory banks. The data items are distributed among the plurality of memory banks, including selecting memory banks in which to store the data items based on pseudorandom numbers generated for the data items, where the pseudorandom numbers are generated using a first pseudorandom number generator initialized with a first seed. Subsequently the data items are retrieved from the plurality of memory banks, including selecting memory banks from which to retrieve the data items based on the pseudorandom numbers regenerated for the data items, where the pseudorandom numbers are regenerated using a second pseudorandom number generator initialized with the first seed.

Aspects of the present disclosure involve a system and method for verifying and validating accurate memory module placement on a printed circuit board. In one embodiment, the printed circuit board is configured to include actuating elements that can be used to verify correct memory module location placement on the printed circuit board. In another embodiment, the actuating elements can be used to validate accurate memory module placement. The actuating elements can be in the form of buttons that may be depressed and configured to trigger light emitting diodes (LEDs) that correspond to the slots on the printed circuit board.

A memory system has a memory management unit (MMU) that is configured to receive data for storage into physical memory comprising a plurality of memory devices. The MMU receives a logical memory address and converts the logical memory address into at least one page address associated with data to be written to or read from physical memory. The MMU has an address translation circuit that is configured to translate each page address into a physical memory address. In translating the page address, the MMU employs an integer division operation that does not constrain the size of an arbitration map used to define the physical memory address. Thus, the operation of the memory can be better optimized using circuitry that has relatively low complexity and cost.

A system and method for providing dynamic I/O virtualization is herein disclosed. According to one embodiment, a device capable of performing hypervisor-agnostic and device-agnostic I/O virtualization includes a host computer interface, memory, I/O devices (GPU, disk, NIC), and efficient communication mechanisms for virtual machines to communicate their intention to perform I/O operations on the device. According to one embodiment, the communication mechanism may use shared memory. According to some embodiments, the device may be implemented purely in hardware, in software, or using a combination of hardware and software. According to some embodiments, the device may share its memory with guest processes to perform optimizations including but not limited to a shared page cache and a shared heap.

A memory module having different types of memory mounted together on a double-sided substrate has a first edge and opposite second edge and includes a plurality of memory controllers, a plurality of flash memories, and a plurality of second memories having a higher signal transmission rate than the flash memories. A socket terminal for connecting the double-sided substrate to a motherboard is formed on the front surface and the back surface of the double-sided substrate on the first edge side; the memory controllers are disposed on the second edge side; the second memories are disposed on the second edge side at positions opposite the positions at which the memory controllers are disposed; and the flash memories are disposed on at least the back surface thereof at positions that are closer to the first edge than are the positions at which the memory controllers and the second memories are disposed.

Various embodiments of systems and methods to efficiently use a compute element to process a plurality of values distributed over a plurality of servers using a plurality of keys. In various embodiments, a system is configured to identify (or derive) the various server locations of various data values, to send requests to the various servers for the needed data values, to receive the data values from the various servers, and to process the various data values received. In various embodiments, requests are sent and data values are received via a switching network. In various embodiments, the servers are organized in a key value store, which may optionally be a shared memory pool. Various embodiments are systems and methods with a small number of compute elements and servers, but in alternative embodiments the elements may be expanded to hundreds or thousands of compute elements and servers.

The present disclosure includes methods and apparatuses for read cache memory. One apparatus includes a read cache memory apparatus comprising a first DRAM array, a first and a second NAND array, and a controller configured to manage movement of data between the DRAM array and the first NAND array, and between the first NAND array and the second NAND array.