Provided are an apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device having a 2.sup.n cache size. A request is to a target address having n bits directed to the second level memory device. A determination is made whether a target index, comprising m bits of the n bits of the target address, is within an index set of the first level memory device. A determination is made of a modified target index in the index set of the first level memory device having at least one index bit that differs from a corresponding at least one index bit in the target index. The request is processed with respect to data in a cache line at the modified target index in the first level memory device.

Various systems and methods to achieve load balancing among a plurality of compute elements accessing a shared memory pool. The shared memory pool is configured to store and serve a plurality of data sets associated with a task, a first data interface's internal registry is configured to keep track of which data sets have been extracted from the shared memory pool and served to the compute elements, the first data interface is configured to extract from the shared memory pool and serve to the compute elements data sets which have not yet been extracted and served, the rate at which data sets are extracted and served to each particular compute element is proportional to the rate at which that compute element requests data sets, and the system may continues to extract, serve, and process data sets until all of the data sets associated with the task have been processed once.

Various embodiments of systems and methods to allow and control simultaneous access and processing by multiple compute elements of multiple data sets stored in multiple memory modules. The compute elements request data to be processed without specifying any particular data sets to be received. Data interfaces receive the data requests from the compute elements, determine which data sets have not yet been served to the compute elements, select data sets to be served from among those that have not yet been served, and fetch these data sets from the memory modules. The process of requesting additional data by the compute elements, selection by the data interfaces of data sets to be served among those that have not yet been served, and providing such data sets by the data interfaces to the compute elements, may continue until all of the data sets have been served to the compute elements.

The present disclosure includes methods and apparatuses for read cache memory. One apparatus includes a read cache memory apparatus comprising a first DRAM array, a first and a second NAND array, and a controller configured to manage movement of data between the DRAM array and the first NAND array, and between the first NAND array and the second NAND array.

Provided are an apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device having a 2.sup.n cache size. A request is to a target address having n bits directed to the second level memory device. A determination is made whether a target index, comprising m bits of the n bits of the target address, is within an index set of the first level memory device. A determination is made of a modified target index in the index set of the first level memory device having at least one index bit that differs from a corresponding at least one index bit in the target index. The request is processed with respect to data in a cache line at the modified target index in the first level memory device.

A device includes a Standard Bus Interface Circuit (SBIC), a memory interface circuit, a Direct Memory Access (DMA) controller, and an Interlaken Look-Aside (ILA) interface circuit. A search key data set including multiple search keys is received via the SBIC and is written to an external memory via the memory interface circuit. The DMA controller receives a descriptor via the SBIC, generates a search key data request, receives the search key data set, and selects a single search key from the set. The ILA interface circuit receives the search key from the DMA controller, generates and ILA packet including the search key, and sends the ILA packet to an external transactional memory device that generates a result data value. The DMA controller receives the result data value via the ILA interface circuit, writes the result data value to the external memory, and sends a DMA completion notification.

A data storage device includes a storage memory device, a control unit suitable for generating a descriptor, which describes a work for controlling the storage memory device, and storing the descriptor in a working memory, and a memory control unit suitable for generating control signals for the storage memory device by fetching an instruction set from an instruction memory based on the descriptor.

Various systems and methods to perform efficiently a first processing task in conjunction with a plurality of data sets. A first code sequence comprises a plurality of general commands, and a specific command including a description of a first data processing task to be performed in conjunction with the data sets. The general commands are received and processed in a standard manner. The specific command is identified automatically by its nature, and the description within the specific command is then converted into a first sequence of executable instructions executable by a plurality of compute elements holding the plurality of data sets. The ultimate result is an efficient implementation of the first processing task. In some embodiments, the implementation of the first processing task is assisted by a pre-defined procedure that allocates the data sets to the compute elements and shares instances of executable instructions with the compute elements.

Described herein are systems and methods to prevent a controller in a DDIO (data direct input output) system from shifting currently-required data out of a cache memory. In one embodiment, a compute element disables caching of some specific addresses in a non-cache memory, but still enables caching of other addresses in the non-cache memory, thereby practically disabling the DDIO system, so that data sets not currently needed are placed in the addresses in the non-cache memory which are not cached. As a result, currently-required data are not shifted out of cache memory. The compute element then determines that the data sets, which formerly avoided being cached, are now required. The system therefore copies the data sets that are now required from addresses in non-cache memory not accessible to cache memory, to addresses in non-cache memory accessible to cache memory, thereby allowing the caching and processing of such data sets.

A memory manager in a computing device allocates memory to programs running on the computing device, the amount of memory allocated to a program being a memory commit for the program. When a program is in a state where the program can be terminated, the content of the memory pages allocated to the program is compressed, and an amount of the memory commit for the program that can be released is determined. This amount of memory commit is the amount that was committed to the program less any amount still storing (in compressed format) information (e.g., data or instructions) for the program. The determined amount of memory commit is released, allowing that amount of memory to be consumed by other programs as appropriate.