A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

The present application discloses a data transmission method and apparatus. Multiple first data blocks of one service are received by a network interface card and the card allocates the received multiple first data blocks to a same data queue. When a tuner generates scheduling information for the service, the multiple first data blocks is sent to a virtual machine by using a resource in a resource pool of a NUMA node designated in the scheduling information; or when a tuner does not generate scheduling information, determining, according to a correspondence between the data queue and a resource pool of a NUMA node, a resource pool corresponding to the data queue in which the multiple first data blocks are located, and sending the multiple first data blocks to a virtual machine.

Local memory and disaggregated memory may be identified and monitored for integrating disaggregated memory in a computing system. Candidate data may be migrated between the local memory and disaggregated memory to optimize allocation of disaggregated memory and migrated data according to a dynamic set of migration criteria.

A sub-Non-Uniform Memory Access (sub-NUMA) clustering fault resilient memory system includes an initialization subsystem that is coupled to a processing system and a memory system. The initialization subsystem determines that the processing system and the memory system are configured to provide a plurality of NUMA nodes, allocates a respective portion of the memory system to each of the plurality of NUMA nodes, and configures each respective portion of the memory system to mirror a mirrored subset of that respective portion of the memory system. Subsequently, respective data that is utilized by each of the plurality of NUMA nodes provided by the processing system and the memory system and that is stored in the mirrored subset of the respective portion of the memory system allocated to that NUMA node is mirrored in that respective portion of the memory system.

Embodiments of the invention provide systems and methods to implement an object memory fabric. Object memory modules may include object storage storing memory objects, memory object meta-data, and a memory module object directory. Each memory object and/or memory object portion may be created natively within the object memory module and may be a managed at a memory layer. The memory module object directory may index all memory objects and/or portions within the object memory module. A hierarchy of object routers may communicatively couple the object memory modules. Each object router may maintain an object cache state for the memory objects and/or portions contained in object memory modules below the object router in the hierarchy. The hierarchy, based on the object cache state, may behave in aggregate as a single object directory communicatively coupled to all object memory modules and to process requests based on the object cache state.

A data processing apparatus comprises processing circuitry to execute a plurality of processes. An ownership table comprises one or more entries each indicating, for a corresponding block of physical addresses, which of the processes is an owner process that has exclusive control of access to the corresponding block of physical addresses. A new process may be prevented from becoming an owner process until after successful completion of destructive overwriting. Ownership protection circuitry may detect a mismatch between an expected attribute, which is dependent on information in a page table entry, and an attribute specified in the ownership table. Each entry in the ownership table, for example, may indicate a level of encryption to be applied. Access control circuitry such as a memory management unit (MMU) may also determine whether an access request satisfies access permissions. The ownership table may also specify whether a higher privilege level process is allowed to access a block of physical addresses. A descriptor table may be used to store process state identifiers, where the process states may include invalid, prepare and execute states. The processes may comprise a hypervisor and/or a virtual machine (VM).

A system includes a central processing unit (CPU) including semiconductor dies, wherein each semiconductor die includes processing cores. The system includes a multi-host network interface card (NIC). The NIC includes an external connection interface circuit and CPU interface circuits. The NIC is coupled to an external data source through the external connection interface circuit and to each the semiconductor dies through a respective CPU interface circuit. The NIC is configured to receive data from the external data source for a different peripherals separately connected to semiconductor dies, and route the data for peripherals through respective CPU interface circuits.

Embodiments of the invention provide systems and methods for managing processing, memory, storage, network, and cloud computing to significantly improve the efficiency and performance of processing nodes. More specifically, embodiments of the present invention are directed to an instruction set of an object memory fabric. This object memory fabric instruction set can be used to provide a unique instruction model based on triggers defined in metadata of the memory objects. This model represents a dynamic dataflow method of execution in which processes are performed based on actual dependencies of the memory objects. This provides a high degree of memory and execution parallelism which in turn provides tolerance of variations in access delays between memory objects. In this model, sequences of instructions are executed and managed based on data access. These sequences can be of arbitrary length but short sequences are more efficient and provide greater parallelism.

The present application presents a Uniform Memory Access (UMA) network including a cluster of UMA nodes. A system in a UMA node comprises persistent memory; non-persistent memory, a node control device operatively coupled to the persistent memory and the non-persistent memory, a local interface for interfacing with the local server in the respective UMA node, and a network interface for interfacing with the UMA network. The node control device is configured to translate between a local unified memory access (UMA) address space accessible by applications running on a local server and a global UMA address space that is mapped to a physical UMA address space. The physical UMA address space includes physical address spaces associated with different UMA nodes in the cluster of UMA nodes. Thus, a server in the UMA network can access the physical address spaces at other UMA nodes without going through the servers in the other UMA nodes.

An address range mirroring system includes a plurality of processing subsystem/memory subsystem nodes that each include a respective processing subsystem coupled to a respective memory subsystem, an operating system provided by at least one of the plurality of processing subsystem/memory subsystem nodes, and a Basic Input/Output System (BIOS) that is coupled to the plurality of processing subsystem/memory subsystem nodes. The BIOS identifies an address range mirroring memory size that was provided by the operating system, and an address range mirroring node usage identification that was provided by the operating system. The BIOS then configures address range mirroring according to the address range mirroring memory size in the respective memory subsystem in each of a subset of the plurality of processing subsystem/memory subsystem nodes, with the subset of the plurality of processing subsystem/memory subsystem nodes based on the address range mirroring node usage identification.