Techniques described herein generally include methods and systems related to cache partitioning in a chip multiprocessor. Cache-partitioning for a single thread or application between multiple data sources improves energy or latency efficiency of a chip multiprocessor by exploiting variations in energy cost and latency cost of the multiple data sources. Partition sizes for each data source may be selected using an optimization algorithm that minimizes or otherwise reduces latencies or energy consumption associated with cache misses.

Embodiments relate to providing a configurable cache memory. An aspect includes configuring, via a cache configuration logic, a plurality of cache memories that make up the configurable cache memory into a selected mode, wherein the plurality of cache memories comprise physically separate memory modules, and wherein the plurality of cache memories are linked by the cache configuration logic. Another aspect includes operating the configurable cache memory in the selected mode, wherein the configurable cache memory is capable of operating in a plurality of modes.

Embodiments relate to providing a configurable cache memory. An aspect includes configuring, via a cache configuration logic, a plurality of cache memories that make up the configurable cache memory into a selected mode, wherein the plurality of cache memories comprise physically separate memory modules, and wherein the plurality of cache memories are linked by the cache configuration logic. Another aspect includes operating the configurable cache memory in the selected mode, wherein the configurable cache memory is capable of operating in a plurality of modes.

A data storage system may be configured at least with a primary memory that is coupled to a host via a controller and coupled to at least one external interface. The controller may be adapted to passively partition a secondary memory into cache and user memory space regions in response to the secondary memory engaging the at least one external interface and the cache region can be allocated as cache for the primary memory by the controller.

Systems and methods for adaptive implementation of victim cache modes in a portable computing device (PCD) are presented. In operation, an upper level cache is partitioned into a main portion and a sample portion; and a lower level cache is partitioned into a corresponding main portion and sample portion in communication with the main portion and sample portion of the upper level cache. A victim mode sample data set and a normal mode sample data set are obtained from the lower level cache. Based on the victim mode and a normal mode sample data sets, a determination is made whether to operate the lower level cache as a victim to the upper level cache. The main portion of lower level cache is caused to operate either as a victim or non-victim to the main portion of the upper level cache in accordance with the determination.

Provided is a method of data storage, the method including receiving, at a host of a key-value store, a request to access a data node stored on a storage device of the key-value store, locating an address corresponding to the data node in a host cache on the host, and determining that the data node is in a kernel cache on the storage device.

Treating main memory as a collection of tagged cache lines for trace logging. A computer system allocates a plurality of memory blocks, and a corresponding plurality of tags, within a main memory. Each tag indicates whether data stored in a corresponding memory block has been captured by an execution trace. The computer system synchronizes these tags with tags in a memory cache and manages a traced status of the memory blocks. This can include one or more of (i) setting a tag to indicate a memory block has not been captured based on identifying a direct memory access operation, (ii) setting a tag based on whether a paged-in value of a memory block has been captured, (iii) setting a tag or memory categorization based whether a memory block has been initialized, or (iv) setting a tag or memory categorization based whether a memory block is mapped to a file.