An apparatus includes an operand cache for storing operands from a register file for use by execution circuitry. In some embodiments, eviction priority for the operand cache is based on the status of entries (e.g., whether dirty or clean) and the retention priority of entries. In some embodiments, flushes are handled differently based on their retention priority (e.g., low-priority entries may be pre-emptively flushed). In some embodiments, timing for cache clean operations is specified on a per-instruction basis. Disclosed techniques may spread out write backs in time, facilitate cache clean operations, facilitate thread switching, extend the time operands are available in an operand cache, and/or improve the use of compiler hints, in some embodiments

A method and system for efficiently executing a delegate of a program by a processor coupled to an external memory. A payload including state data or command data is bound with a program delegate. The payload is mapped with the delegate via the payload identifier. The payload is pushed to a repository buffer in the external memory. The payload is flushed by reading the payload identifier and loading the payload from the repository buffer. The delegate is executed using the loaded payload.

In an example, an apparatus comprises a plurality of compute engines; and logic, at least partially including hardware logic, to detect a cache line conflict in a last-level cache (LLC) communicatively coupled to the plurality of compute engines; and implement context-based eviction policy to determine a cache way in the cache to evict in order to resolve the cache line conflict. Other embodiments are also disclosed and claimed.

A method for cache entry replacement can include monitoring, by at least one physical processor, a first utilization of a first set of cache entries of a cache and a second utilization of a second set of cache entries of the cache. The method can additionally include selecting, by the at least one physical processor and in response to the monitoring, a first replacement policy for the first set of cache entries and a second replacement policy for the second set of cache entries. The method can also include simultaneously applying, by the at least one physical processor and in response to the selecting, the first replacement policy when performing cache entry replacement in the first set of cache entries and the second replacement policy when performing cache entry replacement in the second set of cache entries. Various other methods and systems are also disclosed.