G06F2212/6046

SELECTIVE BYPASSING OF ALLOCATION IN A CACHE

Systems and methods are directed to selectively bypassing allocation of cache lines in a cache. A bypass predictor table is provided with reuse counters to track reuse characteristics of cache lines, based on memory regions to which the cache lines belong in memory. A contender reuse counter provides an indication of a likelihood of reuse of a contender cache line in the cache pursuant to a miss in the cache for the contender cache line, and a victim reuse counter provides an indication of a likelihood of reuse for a victim cache line that will be evicted if the contender cache line is allocated in the cache. A decision whether to allocate the contender cache line in the cache or bypass allocation of the contender cache line in the cache is based on the contender reuse counter value and the victim reuse counter value.

Cache lookup bypass in multi-level cache systems

Techniques described herein are generally related to retrieval of data in computer systems having multi-level caches. The multi-level cache may include at least a first cache and a second cache. The first cache may be configured to receive a request for a cache line. The request may be associated with an instruction executing on a tile of the computer system. A suppression status of the instruction may be determined by a first cache controller to determine whether look-up of the first cache is suppressed based upon the determined suppression status. The request for the cache line may be forwarded to the second cache by the first cache controller after the look-up of the first cache is suppressed.

Partitioning TLB or cache allocation
11243892 · 2022-02-08 · ·

A request for data from a cache (TLB or data/instruction cache) specifies a partition identifier allocated to a software execution environment associated with the request. Allocation of data to the cache is controlled based on a set of configuration information selected based on the partition identifier specified by the request. For a TLB, this allows different allocation policies to be used for requests associated with different software execution environments. In one example, the cache allocation is controlled based on an allocation threshold specified by the selected set of configuration information, which limits the maximum number of cache entries allowed to be allocated with data associated with the corresponding partition identifier.

Apparatus, system and method for providing a persistent level-two cache

Aspects of the present disclosure involve a level-two persistent cache. In various aspects, a solid-state drive is employed as a level-two cache to expand the capacity of existing caches. In particular, any data that is scheduled to be evicted or otherwise removed from a level-one cache is stored in the level-two cache with corresponding metadata in a manner that is quickly retrievable.

Dynamic hierarchical memory cache awareness within a storage system

A computing device-implemented method for implementing dynamic hierarchical memory cache (HMC) awareness within a storage system is described. Specifically, when performing dynamic read operations within a storage system, a data module evaluates a data prefetch policy according to a strategy of determining if data exists in a hierarchical memory cache and thereafter amending the data prefetch policy, if warranted. The system then uses the data prefetch policy to perform a read operation from the storage device to minimize future data retrievals from the storage device. Further, in a distributed storage environment that include multiple storage nodes cooperating to satisfy data retrieval requests, dynamic hierarchical memory cache awareness can be implemented for every storage node without degrading the overall performance of the distributed storage environment.

Just-in-time data provision based on predicted cache policies

Systems, and methods are provided for predicting a cache policy based on application input data. Inputs provided to an application and corresponding to a usage pattern of the application can be received. The inputs can be used with a predictive model to determine a cache policy corresponding to a datastore. The cache policy can include output data to be provided via in the datastore and subsequently provided to a computing device in a just-in-time manner. The predictive model can be trained to output the cache policy based on input data received from a usage point, a provider point, or a datastore configuration.

WRITE-ALLOCATION FOR A CACHE BASED ON EXECUTE PERMISSIONS

Systems and methods for managing access to a cache relate to determining one or more execute permissions associated with a write-address of a write-request to the cache. The cache may be a unified cache for storing data as well as instructions. If there is a write-miss in the cache for the write-request, a cache controller may determine whether to implement a write-allocate policy or a write-no-allocate policy for servicing the write-miss, based on the one or more execute permissions. The one or more execute permissions can relate to a privilege level associated with the write-address. Execute permissions of a producing agent which generated the write-request and an execute permission of a consuming agent which can execute from the write-address may be based on the privilege levels of the producing agent and the consuming agent, respectively.

Method and system for performing data movement operations with read snapshot and in place write update

Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.

Interface circuitry for exchanging information with master, home, and slave nodes using different data transfer protocols

A data processing system comprises a master node to initiate data transmissions; one or more slave nodes to receive the data transmissions; and a home node to control coherency amongst data stored by the data processing system; in which at least one data transmission from the master node to one of the one or more slave nodes bypasses the home node.

I/O behavior prediction based on long-term pattern recognition

Described herein is a system, and related techniques, for predicting I/O requests that are not necessarily directed to sequential sectors of a physical storage device. In some embodiments, I/O patterns that do not involve sequential-sector access, and that may be relatively long-term patterns, may be recognized. To recognize such patterns, deep machine-learning techniques may be used, for example, using neural networks. Such neural networks may be a recurrent neural network such as, for example, an LSTM-RNN. I/O streams for a workstream may be sampled for specific I/O features to produce a time series of I/O feature values of a workstream, and this time series of data may be fed to a prediction engine, e.g., an LSTM-RNN to predict one or more future I/O features values, and I/O actions may be taken based on these predicted feature values.